Lines Matching +full:1 +full:- +full:bit +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0+
7 /* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200.
46 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0, \
47 1, 4)
55 #define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)
61 #define SD10G_LANE_LANE_01_CFG_RXDET_STR BIT(5)
69 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0, \
70 1, 4)
72 #define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0)
78 #define SD10G_LANE_LANE_02_CFG_EN_MAIN BIT(1)
84 #define SD10G_LANE_LANE_02_CFG_EN_DLY BIT(2)
90 #define SD10G_LANE_LANE_02_CFG_EN_DLY2 BIT(3)
104 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \
105 1, 4)
107 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0)
115 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \
116 1, 4)
126 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \
127 1, 4)
129 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0)
135 #define SD10G_LANE_LANE_06_CFG_PD_CLK BIT(1)
141 #define SD10G_LANE_LANE_06_CFG_PD_CML BIT(2)
147 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN BIT(3)
153 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4)
159 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH BIT(5)
167 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \
168 1, 4)
176 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4)
182 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN BIT(5)
188 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE BIT(6)
194 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ BIT(7)
202 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \
203 1, 4)
205 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0)
211 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ BIT(1)
217 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE BIT(2)
223 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ BIT(3)
229 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4)
235 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ BIT(5)
241 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS BIT(6)
247 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12 BIT(7)
255 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \
256 1, 4)
258 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0)
264 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4)
272 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \
273 1, 4)
281 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4)
287 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN BIT(5)
293 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN BIT(6)
301 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \
302 1, 4)
312 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \
313 1, 4)
315 #define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0)
321 #define SD10G_LANE_LANE_13_CFG_PHID_1T BIT(1)
327 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN BIT(2)
335 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \
336 1, 4)
346 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \
347 1, 4)
357 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \
358 1, 4)
368 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\
369 1, 4)
371 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0)
377 #define SD10G_LANE_LANE_1A_CFG_PI_EN BIT(1)
383 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN BIT(2)
389 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS BIT(3)
403 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\
404 1, 4)
414 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\
415 1, 4)
417 #define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0)
423 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG BIT(1)
429 #define SD10G_LANE_LANE_23_CFG_DFECK_EN BIT(2)
435 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD BIT(3)
449 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\
450 1, 4)
466 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\
467 1, 4)
477 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\
478 1, 4)
494 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\
495 1, 4)
497 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0)
511 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\
512 1, 4)
514 #define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0)
520 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN BIT(1)
526 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG BIT(2)
532 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN BIT(3)
538 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4)
544 #define SD10G_LANE_LANE_31_CFG_R50_EN BIT(5)
552 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\
553 1, 4)
555 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)
569 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\
570 1, 4)
586 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\
587 1, 4)
589 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0)
603 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\
604 1, 4)
606 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)
612 #define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4)
618 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH BIT(5)
624 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL BIT(6)
630 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB BIT(7)
638 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\
639 1, 4)
641 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0)
647 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE BIT(1)
653 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF BIT(2)
667 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\
668 1, 4)
676 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4)
684 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\
685 1, 4)
701 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\
702 1, 4)
704 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0)
710 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER BIT(1)
718 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\
719 1, 4)
729 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\
730 1, 4)
740 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\
741 1, 4)
757 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \
758 1, 4)
766 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4)
772 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ BIT(5)
780 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\
781 1, 4)
783 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0)
789 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4)
795 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL BIT(5)
801 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL BIT(6)
807 #define SD10G_LANE_LANE_50_CFG_JT_EN BIT(7)
815 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \
816 1, 4)
826 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60, \
827 0, 1, 4)
829 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0)
835 #define SD10G_LANE_LANE_83_R_TX_POL_INV BIT(1)
841 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE BIT(2)
847 #define SD10G_LANE_LANE_83_R_RX_POL_INV BIT(3)
853 #define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4)
859 #define SD10G_LANE_LANE_83_R_CDR_RSTN BIT(5)
865 #define SD10G_LANE_LANE_83_R_CTLE_RSTN BIT(6)
873 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\
874 1, 4)
876 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0)
882 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)
888 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE BIT(2)
894 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL BIT(3)
900 #define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4)
906 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT BIT(5)
912 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT BIT(6)
918 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)
926 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\
927 1, 4)
935 #define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4)
941 #define SD10G_LANE_LANE_94_R_TXEQ_REG BIT(5)
947 #define SD10G_LANE_LANE_94_R_MISC_REG BIT(6)
953 #define SD10G_LANE_LANE_94_R_SWING_REG BIT(7)
961 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\
962 1, 4)
964 #define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0)
970 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)
976 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN BIT(2)
984 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\
985 1, 4)
987 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)
993 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4)
999 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT BIT(5)
1005 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)
1011 #define SD10G_LANE_LANE_A1_R_PCLK_GATING BIT(7)
1019 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\
1020 1, 4)
1030 __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\
1031 1, 4)
1033 #define SD10G_LANE_LANE_DF_LOL_UDL BIT(0)
1039 #define SD10G_LANE_LANE_DF_LOL BIT(1)
1045 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
1051 #define SD10G_LANE_LANE_DF_SQUELCH BIT(3)
1057 /* SPARX5 ONLY */
1060 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
1062 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0)
1068 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY BIT(1)
1074 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET BIT(2)
1080 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD BIT(3)
1092 /* SPARX5 ONLY */
1095 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
1097 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0)
1103 #define SD25G_LANE_CMU_0B_CFG_DISLOL BIT(1)
1109 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)
1115 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN BIT(3)
1121 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD BIT(4)
1127 #define SD25G_LANE_CMU_0B_CFG_DISLOS BIT(5)
1133 #define SD25G_LANE_CMU_0B_CFG_DCLOL BIT(6)
1139 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN BIT(7)
1145 /* SPARX5 ONLY */
1148 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)
1150 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0)
1156 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN BIT(1)
1162 #define SD25G_LANE_CMU_0C_CFG_VCO_PD BIT(2)
1168 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP BIT(3)
1180 /* SPARX5 ONLY */
1183 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)
1185 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0)
1191 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN BIT(1)
1197 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP BIT(2)
1203 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP BIT(3)
1215 /* SPARX5 ONLY */
1218 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)
1226 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD BIT(4)
1232 /* SPARX5 ONLY */
1235 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)
1243 #define SD25G_LANE_CMU_13_CFG_JT_EN BIT(4)
1249 /* SPARX5 ONLY */
1252 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)
1254 #define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0)
1260 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET BIT(1)
1266 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET BIT(2)
1278 /* SPARX5 ONLY */
1281 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)
1283 #define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0)
1289 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN BIT(1)
1295 /* SPARX5 ONLY */
1298 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)
1306 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT BIT(4)
1312 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE BIT(5)
1318 #define SD25G_LANE_CMU_1A_R_REG_MANUAL BIT(6)
1324 /* SPARX5 ONLY */
1327 __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)
1329 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0)
1335 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE BIT(4)
1341 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS BIT(5)
1347 /* SPARX5 ONLY */
1350 __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)
1364 /* SPARX5 ONLY */
1367 __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)
1375 /* SPARX5 ONLY */
1378 __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)
1380 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0)
1386 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD BIT(1)
1392 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK BIT(2)
1398 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN BIT(3)
1404 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN BIT(4)
1410 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST BIT(5)
1416 /* SPARX5 ONLY */
1419 __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)
1427 /* SPARX5 ONLY */
1430 __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)
1438 /* SPARX5 ONLY */
1441 __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)
1449 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL BIT(4)
1455 /* SPARX5 ONLY */
1458 __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)
1466 /* SPARX5 ONLY */
1469 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)
1483 /* SPARX5 ONLY */
1486 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)
1500 /* SPARX5 ONLY */
1503 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)
1511 /* SPARX5 ONLY */
1514 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)
1516 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0)
1522 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN BIT(1)
1528 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML BIT(2)
1534 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK BIT(3)
1540 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER BIT(4)
1546 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN BIT(5)
1552 /* SPARX5 ONLY */
1555 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)
1569 /* SPARX5 ONLY */
1572 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)
1574 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0)
1586 /* SPARX5 ONLY */
1589 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)
1591 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0)
1597 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2 BIT(1)
1603 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY BIT(2)
1609 /* SPARX5 ONLY */
1612 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)
1620 /* SPARX5 ONLY */
1623 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)
1631 /* SPARX5 ONLY */
1634 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)
1636 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0)
1642 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST BIT(1)
1654 /* SPARX5 ONLY */
1657 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)
1665 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN BIT(4)
1671 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD BIT(5)
1677 /* SPARX5 ONLY */
1680 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)
1688 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8 BIT(4)
1694 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN BIT(5)
1700 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD BIT(6)
1706 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN BIT(7)
1712 /* SPARX5 ONLY */
1715 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)
1717 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0)
1723 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD BIT(1)
1729 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG BIT(2)
1741 /* SPARX5 ONLY */
1744 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)
1752 /* SPARX5 ONLY */
1755 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)
1757 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0)
1763 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT BIT(1)
1769 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN BIT(2)
1775 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD BIT(3)
1787 /* SPARX5 ONLY */
1790 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)
1792 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0)
1798 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD BIT(1)
1804 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL BIT(2)
1810 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN BIT(3)
1816 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU BIT(4)
1822 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP BIT(5)
1828 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET BIT(6)
1834 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE BIT(7)
1840 /* SPARX5 ONLY */
1843 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)
1845 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0)
1857 /* SPARX5 ONLY */
1860 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)
1868 /* SPARX5 ONLY */
1871 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)
1873 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0)
1879 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD BIT(1)
1885 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD BIT(2)
1897 /* SPARX5 ONLY */
1900 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)
1902 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0)
1908 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD BIT(1)
1914 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN BIT(2)
1920 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP BIT(3)
1926 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T BIT(4)
1932 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN BIT(5)
1938 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR BIT(6)
1944 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD BIT(7)
1950 /* SPARX5 ONLY */
1953 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)
1955 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0)
1961 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN BIT(4)
1967 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN BIT(5)
1973 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR BIT(6)
1979 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD BIT(7)
1985 /* SPARX5 ONLY */
1988 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)
1996 /* SPARX5 ONLY */
1999 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)
2007 /* SPARX5 ONLY */
2010 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)
2018 /* SPARX5 ONLY */
2021 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)
2029 /* SPARX5 ONLY */
2032 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)
2034 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0)
2040 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH BIT(1)
2046 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL BIT(2)
2058 /* SPARX5 ONLY */
2061 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)
2069 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)
2075 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU BIT(5)
2081 /* SPARX5 ONLY */
2084 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)
2092 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER BIT(4)
2098 /* SPARX5 ONLY */
2101 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)
2115 /* SPARX5 ONLY */
2118 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)
2120 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0)
2126 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ BIT(1)
2132 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ BIT(2)
2138 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS BIT(3)
2144 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC BIT(4)
2150 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG BIT(5)
2156 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN BIT(6)
2162 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN BIT(7)
2168 /* SPARX5 ONLY */
2171 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)
2173 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0)
2179 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV BIT(1)
2185 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE BIT(2)
2191 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV BIT(3)
2197 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN BIT(4)
2203 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN BIT(5)
2209 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN BIT(6)
2215 /* SPARX5 ONLY */
2218 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)
2226 /* SPARX5 ONLY */
2229 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)
2237 /* SPARX5 ONLY */
2240 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)
2248 /* SPARX5 ONLY */
2251 __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)
2259 /* SPARX5 ONLY */
2262 __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)
2264 #define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0)
2270 #define SD25G_LANE_LANE_DE_LN_LOL BIT(1)
2276 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)
2282 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI BIT(3)
2288 /* SPARX5 ONLY */
2291 __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)
2293 #define SD6G_LANE_LANE_DF_LOL_UDL BIT(0)
2299 #define SD6G_LANE_LANE_DF_LOL BIT(1)
2305 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
2311 #define SD6G_LANE_LANE_DF_SQUELCH BIT(3)
2319 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4)
2321 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0)
2327 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET BIT(1)
2333 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET BIT(2)
2347 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4)
2349 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0)
2363 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4)
2365 #define SD_CMU_CMU_06_CFG_DISLOS BIT(0)
2371 #define SD_CMU_CMU_06_CFG_DISLOL BIT(1)
2377 #define SD_CMU_CMU_06_CFG_DCLOL BIT(2)
2383 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT BIT(3)
2389 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD BIT(4)
2395 #define SD_CMU_CMU_06_CFG_VCO_PD BIT(5)
2401 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN BIT(6)
2407 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP BIT(7)
2415 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4)
2417 #define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0)
2423 #define SD_CMU_CMU_08_CFG_EN_DUMMY BIT(1)
2429 #define SD_CMU_CMU_08_CFG_CK_TREE_PD BIT(2)
2435 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN BIT(3)
2441 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN BIT(4)
2449 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4)
2451 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0)
2457 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN BIT(1)
2463 #define SD_CMU_CMU_09_CFG_SW_8G BIT(4)
2469 #define SD_CMU_CMU_09_CFG_SW_10G BIT(5)
2477 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4)
2479 #define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0)
2485 #define SD_CMU_CMU_0D_CFG_PD_DIV66 BIT(1)
2491 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD BIT(2)
2497 #define SD_CMU_CMU_0D_CFG_JC_BYP BIT(3)
2503 #define SD_CMU_CMU_0D_CFG_REFCK_PD BIT(4)
2511 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4)
2521 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4)
2523 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0)
2529 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN BIT(1)
2535 #define SD_CMU_CMU_1F_CFG_IC2IP_N BIT(2)
2541 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL BIT(3)
2549 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4)
2551 #define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0)
2559 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4)
2561 #define SD_CMU_CMU_44_R_PLL_RSTN BIT(0)
2567 #define SD_CMU_CMU_44_R_CK_RESETB BIT(1)
2575 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4)
2577 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0)
2583 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT BIT(1)
2589 #define SD_CMU_CMU_45_RESERVED BIT(2)
2595 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT BIT(3)
2601 #define SD_CMU_CMU_45_RESERVED_2 BIT(4)
2607 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT BIT(5)
2613 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT BIT(6)
2619 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN BIT(7)
2627 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4)
2637 __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4)
2645 #define SD_CMU_CMU_E0_PLL_LOL_UDL BIT(4)
2653 __REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \
2656 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0)
2662 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST BIT(1)
2670 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4)
2672 #define SD_LANE_SD_SER_RST_SER_RST BIT(0)
2680 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4)
2682 #define SD_LANE_SD_DES_RST_DES_RST BIT(0)
2690 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4)
2692 #define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0)
2698 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST BIT(1)
2716 #define SD_LANE_SD_LANE_CFG_LANE_RST BIT(8)
2722 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST BIT(9)
2728 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST BIT(10)
2736 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4)
2738 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0)
2744 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE BIT(1)
2758 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4)
2768 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4)
2770 #define SD_LANE_MISC_SD_125_RST_DIS BIT(0)
2776 #define SD_LANE_MISC_RX_ENA BIT(1)
2782 #define SD_LANE_MISC_MUX_ENA BIT(2)
2788 /* SPARX5 ONLY */
2797 __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4)
2811 /* SPARX5 ONLY */
2814 __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)
2816 #define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0)
2822 /* SPARX5 ONLY */
2825 __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)
2827 #define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0)
2833 /* SPARX5 ONLY */
2836 __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)
2838 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0)
2844 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST BIT(1)
2850 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)
2862 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST BIT(8)
2868 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV BIT(9)
2874 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN BIT(10)
2880 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY BIT(11)
2892 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN BIT(16)
2904 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN BIT(22)
2910 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)
2916 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING BIT(24)
2922 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI BIT(25)
2934 /* SPARX5 ONLY */
2937 __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)
3005 /* SPARX5 ONLY */
3008 __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)
3010 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0)
3016 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE BIT(1)
3028 /* SPARX5 ONLY */
3031 __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)