26 #define REG_DIG_GLB_70			0x0070
38 #define  XTP_PCS_IN_FR_RG		BIT(0)
40 #define REG_DIG_GLB_F4			0x00f4
41 #define  XFI_DPHY_PCS_SEL		BIT(0)
43 #define   XFI_DPHY_PCS_SEL_USXGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
46 #define REG_DIG_LN_TRX_40		0x3040
50 #define REG_DIG_LN_TRX_B0		0x30b0
54 #define REG_ANA_GLB_D0			0x90d0
57 #define  XTP_GLB_USXGMII_EN		BIT(0)
118 	mtk_phy_update_bits(xfi_tphy->base + 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);  in mtk_xfi_tphy_setup()
119 	mtk_phy_update_bits(xfi_tphy->base + 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);  in mtk_xfi_tphy_setup()
120 	mtk_phy_update_bits(xfi_tphy->base + 0x2030, 0x500, is_1g ? 0x0 : 0x500);  in mtk_xfi_tphy_setup()
121 	mtk_phy_update_bits(xfi_tphy->base + 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);  in mtk_xfi_tphy_setup()
122 	mtk_phy_update_bits(xfi_tphy->base + 0x2040, 0x340000, is_1g ? 0x200000 : 0x140000);  in mtk_xfi_tphy_setup()
125 	mtk_phy_update_bits(xfi_tphy->base + 0x50f0, 0xc10, is_1g ? 0x410 : is_5g ? 0x800 : 0x400);  in mtk_xfi_tphy_setup()
126 	mtk_phy_update_bits(xfi_tphy->base + 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);  in mtk_xfi_tphy_setup()
129 	mtk_phy_update_bits(xfi_tphy->base + 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);  in mtk_xfi_tphy_setup()
130 	mtk_phy_update_bits(xfi_tphy->base + 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);  in mtk_xfi_tphy_setup()
131 	mtk_phy_update_bits(xfi_tphy->base + 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);  in mtk_xfi_tphy_setup()
132 	mtk_phy_update_bits(xfi_tphy->base + 0x5078, 0xf000400, is_5g ? 0x8000000 :  in mtk_xfi_tphy_setup()
133 									0x7000400);  in mtk_xfi_tphy_setup()
134 	mtk_phy_update_bits(xfi_tphy->base + 0x507c, 0x5000500, is_5g ? 0x4000400 :  in mtk_xfi_tphy_setup()
135 									0x1000100);  in mtk_xfi_tphy_setup()
136 	mtk_phy_update_bits(xfi_tphy->base + 0x5080, 0x1410, is_1g ? 0x400 : is_5g ? 0x1010 : 0x0);  in mtk_xfi_tphy_setup()
137 	mtk_phy_update_bits(xfi_tphy->base + 0x5084, 0x30300, is_1g ? 0x30300 :  in mtk_xfi_tphy_setup()
138 							      is_5g ? 0x30100 :  in mtk_xfi_tphy_setup()
139 								      0x100);  in mtk_xfi_tphy_setup()
140 	mtk_phy_update_bits(xfi_tphy->base + 0x5088, 0x60200, is_1g ? 0x20200 :  in mtk_xfi_tphy_setup()
141 							      is_5g ? 0x40000 :  in mtk_xfi_tphy_setup()
142 								      0x20000);  in mtk_xfi_tphy_setup()
145 	mtk_phy_update_bits(xfi_tphy->base + 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);  in mtk_xfi_tphy_setup()
146 	mtk_phy_update_bits(xfi_tphy->base + 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);  in mtk_xfi_tphy_setup()
147 	mtk_phy_update_bits(xfi_tphy->base + 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);  in mtk_xfi_tphy_setup()
148 	mtk_phy_update_bits(xfi_tphy->base + 0x50a8, 0xee0000, is_5g ? 0x800000 :  in mtk_xfi_tphy_setup()
149 								       0x6e0000);  in mtk_xfi_tphy_setup()
150 	mtk_phy_update_bits(xfi_tphy->base + 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);  in mtk_xfi_tphy_setup()
153 		writel(0x01423342, xfi_tphy->base + 0x00f8);  in mtk_xfi_tphy_setup()
155 		writel(0x00a132a1, xfi_tphy->base + 0x00f8);  in mtk_xfi_tphy_setup()
157 		writel(0x009c329c, xfi_tphy->base + 0x00f8);  in mtk_xfi_tphy_setup()
159 		writel(0x00fa32fa, xfi_tphy->base + 0x00f8);  in mtk_xfi_tphy_setup()
169 	mtk_phy_set_bits(xfi_tphy->base + 0x0030, 0xc00);  in mtk_xfi_tphy_setup()
179 	mtk_phy_update_bits(xfi_tphy->base + 0x30b0, 0x30, 0x20);  in mtk_xfi_tphy_setup()
180 	writel(0x00008a01, xfi_tphy->base + 0x3028);  in mtk_xfi_tphy_setup()
181 	writel(0x0000a884, xfi_tphy->base + 0x302c);  in mtk_xfi_tphy_setup()
182 	writel(0x00083002, xfi_tphy->base + 0x3024);  in mtk_xfi_tphy_setup()
186 		writel(0x00011110, xfi_tphy->base + 0x3010);  in mtk_xfi_tphy_setup()
187 		writel(0x40704000, xfi_tphy->base + 0x3048);  in mtk_xfi_tphy_setup()
189 		writel(0x00022220, xfi_tphy->base + 0x3010);  in mtk_xfi_tphy_setup()
190 		writel(0x0f020a01, xfi_tphy->base + 0x5064);  in mtk_xfi_tphy_setup()
191 		writel(0x06100600, xfi_tphy->base + 0x50b4);  in mtk_xfi_tphy_setup()
193 			writel(0x40704000, xfi_tphy->base + 0x3048);  in mtk_xfi_tphy_setup()
195 			writel(0x47684100, xfi_tphy->base + 0x3048);  in mtk_xfi_tphy_setup()
199 		writel(0x0000c000, xfi_tphy->base + 0x3064);  in mtk_xfi_tphy_setup()
202 	mtk_phy_update_bits(xfi_tphy->base + 0x3050, 0xa8000000,  in mtk_xfi_tphy_setup()
203 			    (interface != PHY_INTERFACE_MODE_10GBASER) ? 0xa8000000 : 0x0);  in mtk_xfi_tphy_setup()
204 	mtk_phy_update_bits(xfi_tphy->base + 0x3054, 0xaa,  in mtk_xfi_tphy_setup()
205 			    (interface != PHY_INTERFACE_MODE_10GBASER) ? 0xaa : 0x0);  in mtk_xfi_tphy_setup()
208 		writel(0x00000f00, xfi_tphy->base + 0x306c);  in mtk_xfi_tphy_setup()
210 		writel(0x22000f00, xfi_tphy->base + 0x306c);  in mtk_xfi_tphy_setup()
212 		writel(0x20200f00, xfi_tphy->base + 0x306c);  in mtk_xfi_tphy_setup()
214 	mtk_phy_update_bits(xfi_tphy->base + 0xa008, 0x10000, da_war ? 0x10000 : 0x0);  in mtk_xfi_tphy_setup()
216 	mtk_phy_update_bits(xfi_tphy->base + 0xa060, 0x50000, use_lynxi_pcs ? 0x50000 : 0x40000);  in mtk_xfi_tphy_setup()
221 			    is_10g ?  XTP_GLB_USXGMII_SEL(0) :  in mtk_xfi_tphy_setup()
284  * * %0 - OK
303 		return 0;  in mtk_xfi_tphy_set_mode()
317  * %0 - OK
328 	return 0;  in mtk_xfi_tphy_reset()
364 	return 0;  in mtk_xfi_tphy_power_off()
384  * * %0       - OK
406 	xfi_tphy->base = devm_platform_ioremap_resource(pdev, 0);  in mtk_xfi_tphy_probe()
411 	xfi_tphy->clocks[0].id = "topxtal";  in mtk_xfi_tphy_probe()