Lines Matching +full:imp +full:- +full:res +full:- +full:offset +full:- +full:value

1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
220 /* CDR Charge Pump P-path current adjustment */
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
248 /* I-path capacitance adjustment for Gen1 */
377 [U3P_EFUSE_TX_IMP] = "tx-imp",
378 [U3P_EFUSE_RX_IMP] = "rx-imp",
383 struct mtk_phy_instance *inst = sf->private; in u2_phy_params_show()
384 struct u2phy_banks *u2_banks = &inst->u2_banks; in u2_phy_params_show()
385 void __iomem *com = u2_banks->com; in u2_phy_params_show()
389 int ret = debugfs_get_aux_num(sf->file); in u2_phy_params_show()
405 if (u2_banks->misc) { in u2_phy_params_show()
406 tmp = readl(u2_banks->misc + U3P_MISC_REG1); in u2_phy_params_show()
443 return single_open(file, u2_phy_params_show, inode->i_private); in u2_phy_params_open()
449 struct seq_file *sf = file->private_data; in u2_phy_params_write()
450 struct mtk_phy_instance *inst = sf->private; in u2_phy_params_write()
451 struct u2phy_banks *u2_banks = &inst->u2_banks; in u2_phy_params_write()
452 void __iomem *com = u2_banks->com; in u2_phy_params_write()
471 if (u2_banks->misc) in u2_phy_params_write()
472 mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1, in u2_phy_params_write()
509 debugfs_create_file_aux_num(u2_phy_files[i], 0644, inst->phy->debugfs, in u2_phy_dbgfs_files_create()
515 struct mtk_phy_instance *inst = sf->private; in u3_phy_params_show()
516 struct u3phy_banks *u3_banks = &inst->u3_banks; in u3_phy_params_show()
520 int ret = debugfs_get_aux_num(sf->file); in u3_phy_params_show()
524 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); in u3_phy_params_show()
530 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); in u3_phy_params_show()
536 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); in u3_phy_params_show()
542 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); in u3_phy_params_show()
559 return single_open(file, u3_phy_params_show, inode->i_private); in u3_phy_params_open()
565 struct seq_file *sf = file->private_data; in u3_phy_params_write()
566 struct mtk_phy_instance *inst = sf->private; in u3_phy_params_write()
567 struct u3phy_banks *u3_banks = &inst->u3_banks; in u3_phy_params_write()
568 void __iomem *phyd = u3_banks->phyd; in u3_phy_params_write()
571 int ret = debugfs_get_aux_num(sf->file); in u3_phy_params_write()
584 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, in u3_phy_params_write()
619 debugfs_create_file_aux_num(u3_phy_files[i], 0644, inst->phy->debugfs, in u3_phy_dbgfs_files_create()
625 struct mtk_phy_instance *inst = sf->private; in phy_type_show()
628 switch (inst->type) { in phy_type_show()
657 debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops); in phy_debugfs_init()
659 switch (inst->type) { in phy_debugfs_init()
682 struct u2phy_banks *u2_banks = &instance->u2_banks; in hs_slew_rate_calibrate()
683 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate()
684 void __iomem *com = u2_banks->com; in hs_slew_rate_calibrate()
690 if (tphy->pdata->version == MTK_PHY_V3) in hs_slew_rate_calibrate()
693 /* use force value */ in hs_slew_rate_calibrate()
694 if (instance->eye_src) in hs_slew_rate_calibrate()
708 if (tphy->pdata->version == MTK_PHY_V1) in hs_slew_rate_calibrate()
709 tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1); in hs_slew_rate_calibrate()
716 /* ignore return value */ in hs_slew_rate_calibrate()
730 tmp = tphy->src_ref_clk * tphy->src_coef; in hs_slew_rate_calibrate()
734 /* if FM detection fail, set default value */ in hs_slew_rate_calibrate()
737 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in hs_slew_rate_calibrate()
738 instance->index, fm_out, calibration_val, in hs_slew_rate_calibrate()
739 tphy->src_ref_clk, tphy->src_coef); in hs_slew_rate_calibrate()
752 struct u3phy_banks *u3_banks = &instance->u3_banks; in u3_phy_instance_init()
753 void __iomem *phya = u3_banks->phya; in u3_phy_instance_init()
754 void __iomem *phyd = u3_banks->phyd; in u3_phy_instance_init()
756 if (instance->type_force_mode) { in u3_phy_instance_init()
761 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, in u3_phy_instance_init()
763 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, in u3_phy_instance_init()
767 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, in u3_phy_instance_init()
769 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, in u3_phy_instance_init()
774 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, in u3_phy_instance_init()
784 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, in u3_phy_instance_init()
795 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); in u3_phy_instance_init()
801 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_pll_26m_set()
802 void __iomem *com = u2_banks->com; in u2_phy_pll_26m_set()
804 if (!tphy->pdata->sw_pll_48m_to_26m) in u2_phy_pll_26m_set()
820 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_init()
821 void __iomem *com = u2_banks->com; in u2_phy_instance_init()
822 u32 index = instance->index; in u2_phy_instance_init()
839 if (tphy->pdata->avoid_rx_sen_degradation) { in u2_phy_instance_init()
860 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); in u2_phy_instance_init()
866 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_power_on()
867 void __iomem *com = u2_banks->com; in u2_phy_instance_power_on()
868 u32 index = instance->index; in u2_phy_instance_power_on()
877 if (tphy->pdata->avoid_rx_sen_degradation && index) { in u2_phy_instance_power_on()
882 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); in u2_phy_instance_power_on()
888 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_power_off()
889 void __iomem *com = u2_banks->com; in u2_phy_instance_power_off()
890 u32 index = instance->index; in u2_phy_instance_power_off()
899 if (tphy->pdata->avoid_rx_sen_degradation && index) { in u2_phy_instance_power_off()
905 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); in u2_phy_instance_power_off()
911 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_exit()
912 void __iomem *com = u2_banks->com; in u2_phy_instance_exit()
913 u32 index = instance->index; in u2_phy_instance_exit()
915 if (tphy->pdata->avoid_rx_sen_degradation && index) { in u2_phy_instance_exit()
926 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_set_mode()
929 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
944 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
950 struct u3phy_banks *u3_banks = &instance->u3_banks; in pcie_phy_instance_init()
951 void __iomem *phya = u3_banks->phya; in pcie_phy_instance_init()
953 if (tphy->pdata->version != MTK_PHY_V1) in pcie_phy_instance_init()
966 /* SSC delta -5000ppm */ in pcie_phy_instance_init()
985 /* Tx Detect Rx Timing: 10us -> 5us */ in pcie_phy_instance_init()
986 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1, in pcie_phy_instance_init()
989 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2, in pcie_phy_instance_init()
994 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); in pcie_phy_instance_init()
1000 struct u3phy_banks *bank = &instance->u3_banks; in pcie_phy_instance_power_on()
1002 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, in pcie_phy_instance_power_on()
1005 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, in pcie_phy_instance_power_on()
1013 struct u3phy_banks *bank = &instance->u3_banks; in pcie_phy_instance_power_off()
1015 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, in pcie_phy_instance_power_off()
1018 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, in pcie_phy_instance_power_off()
1025 struct u3phy_banks *u3_banks = &instance->u3_banks; in sata_phy_instance_init()
1026 void __iomem *phyd = u3_banks->phyd; in sata_phy_instance_init()
1064 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); in sata_phy_instance_init()
1070 struct u2phy_banks *u2_banks = &instance->u2_banks; in phy_v1_banks_init()
1071 struct u3phy_banks *u3_banks = &instance->u3_banks; in phy_v1_banks_init()
1073 switch (instance->type) { in phy_v1_banks_init()
1075 u2_banks->misc = NULL; in phy_v1_banks_init()
1076 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; in phy_v1_banks_init()
1077 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; in phy_v1_banks_init()
1081 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; in phy_v1_banks_init()
1082 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; in phy_v1_banks_init()
1083 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; in phy_v1_banks_init()
1084 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; in phy_v1_banks_init()
1087 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; in phy_v1_banks_init()
1090 dev_err(tphy->dev, "incompatible PHY type\n"); in phy_v1_banks_init()
1098 struct u2phy_banks *u2_banks = &instance->u2_banks; in phy_v2_banks_init()
1099 struct u3phy_banks *u3_banks = &instance->u3_banks; in phy_v2_banks_init()
1101 switch (instance->type) { in phy_v2_banks_init()
1103 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; in phy_v2_banks_init()
1104 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; in phy_v2_banks_init()
1105 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; in phy_v2_banks_init()
1109 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; in phy_v2_banks_init()
1110 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; in phy_v2_banks_init()
1111 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; in phy_v2_banks_init()
1112 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; in phy_v2_banks_init()
1115 dev_err(tphy->dev, "incompatible PHY type\n"); in phy_v2_banks_init()
1123 struct device *dev = &instance->phy->dev; in phy_parse_property()
1125 if (instance->type == PHY_TYPE_USB3) in phy_parse_property()
1126 instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode"); in phy_parse_property()
1128 if (instance->type != PHY_TYPE_USB2) in phy_parse_property()
1131 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12"); in phy_parse_property()
1132 device_property_read_u32(dev, "mediatek,eye-src", in phy_parse_property()
1133 &instance->eye_src); in phy_parse_property()
1134 device_property_read_u32(dev, "mediatek,eye-vrt", in phy_parse_property()
1135 &instance->eye_vrt); in phy_parse_property()
1136 device_property_read_u32(dev, "mediatek,eye-term", in phy_parse_property()
1137 &instance->eye_term); in phy_parse_property()
1139 &instance->intr); in phy_parse_property()
1141 &instance->discth); in phy_parse_property()
1142 device_property_read_u32(dev, "mediatek,pre-emphasis", in phy_parse_property()
1143 &instance->pre_emphasis); in phy_parse_property()
1145 instance->bc12_en, instance->eye_src, in phy_parse_property()
1146 instance->eye_vrt, instance->eye_term, in phy_parse_property()
1147 instance->intr, instance->discth); in phy_parse_property()
1148 dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis); in phy_parse_property()
1154 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_props_set()
1155 void __iomem *com = u2_banks->com; in u2_phy_props_set()
1157 if (instance->bc12_en) /* BC1.2 path Enable */ in u2_phy_props_set()
1160 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) in u2_phy_props_set()
1162 instance->eye_src); in u2_phy_props_set()
1164 if (instance->eye_vrt) in u2_phy_props_set()
1166 instance->eye_vrt); in u2_phy_props_set()
1168 if (instance->eye_term) in u2_phy_props_set()
1170 instance->eye_term); in u2_phy_props_set()
1172 if (instance->intr) { in u2_phy_props_set()
1173 if (u2_banks->misc) in u2_phy_props_set()
1174 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, in u2_phy_props_set()
1178 instance->intr); in u2_phy_props_set()
1181 if (instance->discth) in u2_phy_props_set()
1183 instance->discth); in u2_phy_props_set()
1185 if (instance->pre_emphasis) in u2_phy_props_set()
1187 instance->pre_emphasis); in u2_phy_props_set()
1198 if (!of_property_read_bool(dn, "mediatek,syscon-type")) in phy_type_syscon_get()
1201 ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", in phy_type_syscon_get()
1206 instance->type_sw_reg = args.args[0]; in phy_type_syscon_get()
1207 instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ in phy_type_syscon_get()
1208 instance->type_sw = syscon_node_to_regmap(args.np); in phy_type_syscon_get()
1210 dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", in phy_type_syscon_get()
1211 instance->type_sw_reg, instance->type_sw_index); in phy_type_syscon_get()
1213 return PTR_ERR_OR_ZERO(instance->type_sw); in phy_type_syscon_get()
1219 u32 offset; in phy_type_set() local
1221 if (!instance->type_sw) in phy_type_set()
1224 switch (instance->type) { in phy_type_set()
1242 offset = instance->type_sw_index * BITS_PER_BYTE; in phy_type_set()
1243 regmap_update_bits(instance->type_sw, instance->type_sw_reg, in phy_type_set()
1244 RG_PHY_SW_TYPE << offset, type << offset); in phy_type_set()
1251 struct device *dev = &instance->phy->dev; in phy_efuse_get()
1255 if (!tphy->pdata->sw_efuse_supported) { in phy_efuse_get()
1256 instance->efuse_sw_en = 0; in phy_efuse_get()
1261 instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells"); in phy_efuse_get()
1262 if (!instance->efuse_sw_en) in phy_efuse_get()
1265 switch (instance->type) { in phy_efuse_get()
1267 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); in phy_efuse_get()
1274 if (!instance->efuse_intr) { in phy_efuse_get()
1276 instance->efuse_sw_en = 0; in phy_efuse_get()
1280 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr); in phy_efuse_get()
1285 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); in phy_efuse_get()
1291 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp); in phy_efuse_get()
1297 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp); in phy_efuse_get()
1304 if (!instance->efuse_intr && in phy_efuse_get()
1305 !instance->efuse_rx_imp && in phy_efuse_get()
1306 !instance->efuse_tx_imp) { in phy_efuse_get()
1308 instance->efuse_sw_en = 0; in phy_efuse_get()
1312 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", in phy_efuse_get()
1313 instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); in phy_efuse_get()
1316 dev_err(dev, "no sw efuse for type %d\n", instance->type); in phy_efuse_get()
1317 ret = -EINVAL; in phy_efuse_get()
1325 struct device *dev = &instance->phy->dev; in phy_efuse_set()
1326 struct u2phy_banks *u2_banks = &instance->u2_banks; in phy_efuse_set()
1327 struct u3phy_banks *u3_banks = &instance->u3_banks; in phy_efuse_set()
1329 if (!instance->efuse_sw_en) in phy_efuse_set()
1332 switch (instance->type) { in phy_efuse_set()
1334 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); in phy_efuse_set()
1336 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, in phy_efuse_set()
1337 instance->efuse_intr); in phy_efuse_set()
1341 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS); in phy_efuse_set()
1343 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, in phy_efuse_set()
1344 instance->efuse_tx_imp); in phy_efuse_set()
1345 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); in phy_efuse_set()
1347 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, in phy_efuse_set()
1348 instance->efuse_rx_imp); in phy_efuse_set()
1349 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); in phy_efuse_set()
1351 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, in phy_efuse_set()
1352 instance->efuse_intr); in phy_efuse_set()
1355 dev_warn(dev, "no sw efuse for type %d\n", instance->type); in phy_efuse_set()
1363 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_init()
1366 ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks); in mtk_phy_init()
1372 switch (instance->type) { in mtk_phy_init()
1390 dev_err(tphy->dev, "incompatible PHY type\n"); in mtk_phy_init()
1391 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); in mtk_phy_init()
1392 return -EINVAL; in mtk_phy_init()
1401 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_power_on()
1403 if (instance->type == PHY_TYPE_USB2) { in mtk_phy_power_on()
1406 } else if (instance->type == PHY_TYPE_PCIE) { in mtk_phy_power_on()
1416 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_power_off()
1418 if (instance->type == PHY_TYPE_USB2) in mtk_phy_power_off()
1420 else if (instance->type == PHY_TYPE_PCIE) in mtk_phy_power_off()
1429 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_exit()
1431 if (instance->type == PHY_TYPE_USB2) in mtk_phy_exit()
1434 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); in mtk_phy_exit()
1441 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_set_mode()
1443 if (instance->type == PHY_TYPE_USB2) in mtk_phy_set_mode()
1454 struct device_node *phy_np = args->np; in mtk_phy_xlate()
1458 if (args->args_count != 1) { in mtk_phy_xlate()
1460 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1463 for (index = 0; index < tphy->nphys; index++) in mtk_phy_xlate()
1464 if (phy_np == tphy->phys[index]->phy->dev.of_node) { in mtk_phy_xlate()
1465 instance = tphy->phys[index]; in mtk_phy_xlate()
1471 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1474 instance->type = args->args[0]; in mtk_phy_xlate()
1475 if (!(instance->type == PHY_TYPE_USB2 || in mtk_phy_xlate()
1476 instance->type == PHY_TYPE_USB3 || in mtk_phy_xlate()
1477 instance->type == PHY_TYPE_PCIE || in mtk_phy_xlate()
1478 instance->type == PHY_TYPE_SATA || in mtk_phy_xlate()
1479 instance->type == PHY_TYPE_SGMII)) { in mtk_phy_xlate()
1480 dev_err(dev, "unsupported device type: %d\n", instance->type); in mtk_phy_xlate()
1481 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1484 switch (tphy->pdata->version) { in mtk_phy_xlate()
1494 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1505 return instance->phy; in mtk_phy_xlate()
1545 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1546 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1547 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1548 { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1549 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1550 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1551 { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1558 struct device *dev = &pdev->dev; in mtk_tphy_probe()
1559 struct device_node *np = dev->of_node; in mtk_tphy_probe()
1563 struct resource res; in mtk_tphy_probe() local
1568 return -ENOMEM; in mtk_tphy_probe()
1570 tphy->pdata = of_device_get_match_data(dev); in mtk_tphy_probe()
1571 if (!tphy->pdata) in mtk_tphy_probe()
1572 return -EINVAL; in mtk_tphy_probe()
1574 tphy->nphys = of_get_child_count(np); in mtk_tphy_probe()
1575 tphy->phys = devm_kcalloc(dev, tphy->nphys, in mtk_tphy_probe()
1576 sizeof(*tphy->phys), GFP_KERNEL); in mtk_tphy_probe()
1577 if (!tphy->phys) in mtk_tphy_probe()
1578 return -ENOMEM; in mtk_tphy_probe()
1580 tphy->dev = dev; in mtk_tphy_probe()
1585 if (sif_res && tphy->pdata->version == MTK_PHY_V1) { in mtk_tphy_probe()
1587 tphy->sif_base = devm_ioremap_resource(dev, sif_res); in mtk_tphy_probe()
1588 if (IS_ERR(tphy->sif_base)) { in mtk_tphy_probe()
1590 return PTR_ERR(tphy->sif_base); in mtk_tphy_probe()
1594 if (tphy->pdata->version < MTK_PHY_V3) { in mtk_tphy_probe()
1595 tphy->src_ref_clk = U3P_REF_CLK; in mtk_tphy_probe()
1596 tphy->src_coef = U3P_SLEW_RATE_COEF; in mtk_tphy_probe()
1598 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", in mtk_tphy_probe()
1599 &tphy->src_ref_clk); in mtk_tphy_probe()
1600 device_property_read_u32(dev, "mediatek,src-coef", in mtk_tphy_probe()
1601 &tphy->src_coef); in mtk_tphy_probe()
1614 return -ENOMEM; in mtk_tphy_probe()
1616 tphy->phys[port] = instance; in mtk_tphy_probe()
1624 subdev = &phy->dev; in mtk_tphy_probe()
1625 retval = of_address_to_resource(child_np, 0, &res); in mtk_tphy_probe()
1627 dev_err(subdev, "failed to get address resource(id-%d)\n", in mtk_tphy_probe()
1632 instance->port_base = devm_ioremap_resource(subdev, &res); in mtk_tphy_probe()
1633 if (IS_ERR(instance->port_base)) in mtk_tphy_probe()
1634 return PTR_ERR(instance->port_base); in mtk_tphy_probe()
1636 instance->phy = phy; in mtk_tphy_probe()
1637 instance->index = port; in mtk_tphy_probe()
1641 clks = instance->clks; in mtk_tphy_probe()
1661 .name = "mtk-tphy",
1669 MODULE_DESCRIPTION("MediaTek T-PHY driver");