Lines Matching +full:12 +full:gbps
50 #define PU_TX_BIT BIT(12)
68 #define USE_MAX_PLL_RATE_BIT BIT(12)
107 #define IDLE_SYNC_EN BIT(12)
167 #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12)
194 #define PIN_RESET_COMPHY_BIT BIT(12)
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or in mvebu_a3700_comphy_ethernet_power_on()
716 * PCIe speed 2.5/5 Gbps in mvebu_a3700_comphy_ethernet_power_on()
728 * 12. As long as DFE function needs to be enabled in any mode, in mvebu_a3700_comphy_ethernet_power_on()
938 * 12. Override Speed_PLL value and use MAC PLL in mvebu_a3700_comphy_usb3_power_on()
956 * 14. Set max speed generation to USB3.0 5Gbps in mvebu_a3700_comphy_usb3_power_on()