33 #define COMPHY_LANE2_INDIR_ADDR		0x0
34 #define COMPHY_LANE2_INDIR_DATA		0x4
37 #define COMPHY_LANE2_REGS_BASE		0x200
43 #define COMPHY_LANE_REG_DIRECT(reg)	(((reg) & 0x7FF) << 1)
46 #define COMPHY_POWER_PLL_CTRL		0x01
55 #define REF_FREF_SEL_MASK		GENMASK(4, 0)
56 #define REF_FREF_SEL_SERDES_25MHZ	FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
57 #define REF_FREF_SEL_SERDES_40MHZ	FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
58 #define REF_FREF_SEL_SERDES_50MHZ	FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
59 #define REF_FREF_SEL_PCIE_USB3_25MHZ	FIELD_PREP(REF_FREF_SEL_MASK, 0x2)
60 #define REF_FREF_SEL_PCIE_USB3_40MHZ	FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
62 #define COMPHY_MODE_SATA		FIELD_PREP(COMPHY_MODE_MASK, 0x0)
63 #define COMPHY_MODE_PCIE		FIELD_PREP(COMPHY_MODE_MASK, 0x3)
64 #define COMPHY_MODE_SERDES		FIELD_PREP(COMPHY_MODE_MASK, 0x4)
65 #define COMPHY_MODE_USB3		FIELD_PREP(COMPHY_MODE_MASK, 0x5)
67 #define COMPHY_KVCO_CAL_CTRL		0x02
70 #define SPEED_PLL_VALUE_16		FIELD_PREP(SPEED_PLL_MASK, 0x10)
72 #define COMPHY_DIG_LOOPBACK_EN		0x23
74 #define DATA_WIDTH_10BIT		FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0)
75 #define DATA_WIDTH_20BIT		FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1)
76 #define DATA_WIDTH_40BIT		FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2)
79 #define COMPHY_SYNC_PATTERN		0x24
83 #define COMPHY_SYNC_MASK_GEN		0x25
85 #define PHY_GEN_MAX_USB3_5G		FIELD_PREP(PHY_GEN_MAX_MASK, 0x1)
87 #define COMPHY_ISOLATION_CTRL		0x26
90 #define COMPHY_GEN2_SET2		0x3e
92 #define GS2_TX_SSC_AMP_4128		FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20)
95 						   0x0)
97 						   0x1)
99 						   0x2)
101 						   0x3)
102 #define GS2_RSVD_6_0_MASK		GENMASK(6, 0)
104 #define COMPHY_GEN3_SET2		0x3f
106 #define COMPHY_IDLE_SYNC_EN		0x48
109 #define COMPHY_MISC_CTRL0		0x4F
115 #define COMPHY_SFT_RESET		0x52
119 #define COMPHY_MISC_CTRL1		0x73
122 #define COMPHY_GEN2_SET3		0x112
123 #define GS3_FFE_CAP_SEL_MASK		GENMASK(3, 0)
124 #define GS3_FFE_CAP_SEL_VALUE		FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF)
127 #define COMPHY_PIPE_LANE_CFG0		0x180
128 #define PRD_TXDEEMPH0_MASK		BIT(0)
133 #define COMPHY_PIPE_LANE_CFG1		0x181
139 #define TX_ELEC_IDLE_MODE_EN		BIT(0)
141 #define COMPHY_PIPE_LANE_STAT1		0x183
142 #define TXDCLK_PCLK_EN			BIT(0)
144 #define COMPHY_PIPE_LANE_CFG4		0x188
147 #define COMPHY_PIPE_RST_CLK_CTRL	0x1C1
148 #define PIPE_SOFT_RESET			BIT(0)
153 #define MODE_REFDIV_BY_4		FIELD_PREP(MODE_REFDIV_MASK, 0x2)
155 #define COMPHY_PIPE_TEST_MODE_CTRL	0x1C2
158 #define COMPHY_PIPE_CLK_SRC_LO		0x1C3
159 #define MODE_CLK_SRC			BIT(0)
166 #define COMPHY_PIPE_PWR_MGM_TIM1	0x1D0
169 #define CFG_PM_RXDEN_WAIT_1_UNIT	FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1)
170 #define CFG_PM_RXDLOZ_WAIT_MASK		GENMASK(7, 0)
171 #define CFG_PM_RXDLOZ_WAIT_7_UNIT	FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7)
172 #define CFG_PM_RXDLOZ_WAIT_12_UNIT	FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC)
180 #define COMPHY_RESERVED_REG		0x0E
184 #define COMPHY_PHY_REG(lane, reg)	(((1 - (lane)) * 0x28) + ((reg) & 0x3f))
191 #define COMPHY_PHY_CFG1			0x0
203 #define SERDES_SPEED_1_25_G		0x6
204 #define SERDES_SPEED_3_125_G		0x8
212 #define COMPHY_PHY_STAT1		0x18
213 #define PHY_RX_INIT_DONE_BIT		BIT(0)
218 #define COMPHY_SELECTOR_PHY_REG			0xFC
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
220 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT	BIT(0)
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
246 	/* lane 0 */
247 	MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS),
248 	MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII),
249 	MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX),
250 	MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX),
287 	{ 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 },
288 	{ 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 },
289 	{ 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 },
290 	{ 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC },
291 	{ 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 },
292 	{ 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 },
293 	{ 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 },
294 	{ 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 },
295 	{ 0x104, 0x0C10 }
300 	/* 0       1       2       3       4       5       6       7 */
303 	0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26,	/* 00 */
304 	0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52,	/* 08 */
305 	0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000,	/* 10 */
306 	0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF,	/* 18 */
307 	0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000,	/* 20 */
308 	0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,	/* 28 */
309 	0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/* 30 */
310 	0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100,	/* 38 */
311 	0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00,	/* 40 */
312 	0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A,	/* 48 */
313 	0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001,	/* 50 */
314 	0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF,	/* 58 */
315 	0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000,	/* 60 */
316 	0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002,	/* 68 */
317 	0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780,	/* 70 */
318 	0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000,	/* 78 */
319 	0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000,	/* 80 */
320 	0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210,	/* 88 */
321 	0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F,	/* 90 */
322 	0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651,	/* 98 */
323 	0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000,	/* A0 */
324 	0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/* A8 */
325 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/* B0 */
326 	0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000,	/* B8 */
327 	0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003,	/* C0 */
328 	0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000,	/* C8 */
329 	0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00,	/* D0 */
330 	0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000,	/* D8 */
331 	0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541,	/* E0 */
332 	0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200,	/* E8 */
333 	0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000,	/* F0 */
334 	0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000,	/* F8 */
335 	0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000,	/*100 */
336 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*108 */
337 	0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000,	/*110 */
338 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*118 */
339 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*120 */
340 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*128 */
341 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*130 */
342 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*138 */
343 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*140 */
344 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*148 */
345 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*150 */
346 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*158 */
347 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*160 */
348 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*168 */
349 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*170 */
350 	0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000,	/*178 */
351 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*180 */
352 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*188 */
353 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*190 */
354 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*198 */
355 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1A0 */
356 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1A8 */
357 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1B0 */
358 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1B8 */
359 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1C0 */
360 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1C8 */
361 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1D0 */
362 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1D8 */
363 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1E0 */
364 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1E8 */
365 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1F0 */
366 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000	/*1F8 */
470 	u32 old, new, clr = 0, set = 0;  in mvebu_a3700_comphy_set_phy_selector()
483 		if (lane->id == 0)  in mvebu_a3700_comphy_set_phy_selector()
494 		else if (lane->id == 0)  in mvebu_a3700_comphy_set_phy_selector()
521 		"COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n",  in mvebu_a3700_comphy_set_phy_selector()
524 	return 0;  in mvebu_a3700_comphy_set_phy_selector()
544 			    0x0, PHY_ISOLATE_MODE);  in mvebu_a3700_comphy_sata_power_on()
546 	/* 0. Check the Polarity invert bits */  in mvebu_a3700_comphy_sata_power_on()
547 	data = 0x0;  in mvebu_a3700_comphy_sata_power_on()
575 			    0x0, PHYCTRL_FRM_PIN_BIT);  in mvebu_a3700_comphy_sata_power_on()
582 	 *   reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);  in mvebu_a3700_comphy_sata_power_on()
583 	 *   reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));  in mvebu_a3700_comphy_sata_power_on()
605 	fix_idx = 0;  in comphy_gbe_phy_init()
606 	for (addr = 0; addr < ARRAY_SIZE(gbe_phy_init); addr++) {  in comphy_gbe_phy_init()
624 		comphy_lane_reg_set(lane, addr, val, 0xFFFF);  in comphy_gbe_phy_init()
643 	 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.  in mvebu_a3700_comphy_ethernet_power_on()
650 	/* 4. Release reset to the PHY by setting PIN_RESET=0. */  in mvebu_a3700_comphy_ethernet_power_on()
651 	data = 0x0;  in mvebu_a3700_comphy_ethernet_power_on()
656 	 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY  in mvebu_a3700_comphy_ethernet_power_on()
695 	data = 0x0;  in mvebu_a3700_comphy_ethernet_power_on()
712 	 * 10. Program COMPHY register PHY_GEN_MAX[1:0]  in mvebu_a3700_comphy_ethernet_power_on()
729 	 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F  in mvebu_a3700_comphy_ethernet_power_on()
731 	 * The value of the DFE_UPDATE_EN already is 0x3F, because it is the  in mvebu_a3700_comphy_ethernet_power_on()
753 	data = 0x0;  in mvebu_a3700_comphy_ethernet_power_on()
786 	 * 17. Set COMPHY input port PIN_TX_IDLE=0  in mvebu_a3700_comphy_ethernet_power_on()
788 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);  in mvebu_a3700_comphy_ethernet_power_on()
792 	 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the  in mvebu_a3700_comphy_ethernet_power_on()
794 	 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please  in mvebu_a3700_comphy_ethernet_power_on()
835 	 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The  in mvebu_a3700_comphy_usb3_power_on()
851 	 *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db  in mvebu_a3700_comphy_usb3_power_on()
852 	 *            together with bit 0 of COMPHY_PIPE_LANE_CFG0 register  in mvebu_a3700_comphy_usb3_power_on()
870 			    MODE_MARGIN_OVERRIDE, 0xFFFF);  in mvebu_a3700_comphy_usb3_power_on()
876 	data = 0x0;  in mvebu_a3700_comphy_usb3_power_on()
935 			    DATA_WIDTH_20BIT, 0xFFFF);  in mvebu_a3700_comphy_usb3_power_on()
941 	mask = 0xFFFF;  in mvebu_a3700_comphy_usb3_power_on()
947 	data = 0x0;  in mvebu_a3700_comphy_usb3_power_on()
956 	 * 14. Set max speed generation to USB3.0 5Gbps  in mvebu_a3700_comphy_usb3_power_on()
962 	 * 15. Set capacitor value for FFE gain peaking to 0xF  in mvebu_a3700_comphy_usb3_power_on()
971 	mask = 0xFFFF;  in mvebu_a3700_comphy_usb3_power_on()
1024 	 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in  in mvebu_a3700_comphy_pcie_power_on()
1040 	mask = 0xFFFF;  in mvebu_a3700_comphy_pcie_power_on()
1046 			    0xFFFF);  in mvebu_a3700_comphy_pcie_power_on()
1049 	data = 0x0;  in mvebu_a3700_comphy_pcie_power_on()
1082 			    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);  in mvebu_a3700_comphy_sata_power_off()
1101 			    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);  in mvebu_a3700_comphy_pcie_power_off()
1118 	/* Unused PHY mux value is 0x0 */  in mvebu_a3700_comphy_check_mode()
1122 	for (i = 0; i < n; i++) {  in mvebu_a3700_comphy_check_mode()
1154 	return 0;  in mvebu_a3700_comphy_set_mode()
1191 	case 0:  in mvebu_a3700_comphy_power_off()
1194 		return 0;  in mvebu_a3700_comphy_power_off()
1198 		return 0;  in mvebu_a3700_comphy_power_off()
1202 		return 0;  in mvebu_a3700_comphy_power_off()
1229 	port = args->args[0];  in mvebu_a3700_comphy_xlate()
1230 	if (port != 0 && (port != 1 || lane->id != 0)) {  in mvebu_a3700_comphy_xlate()
1235 	lane->invert_tx = args->args[1] & BIT(0);  in mvebu_a3700_comphy_xlate()
1312 		if (ret < 0) {  in mvebu_a3700_comphy_probe()