3  * PCIe phy driver for Kirin 970
29 #include <linux/phy/phy.h>
49 /* PCIe PHY registers */
173 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,  in hi3670_apb_phy_writel()  argument
176 	writel(val, phy->base + APB_PHY_START_ADDR + reg);  in hi3670_apb_phy_writel()
179 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)  in hi3670_apb_phy_readl()  argument
181 	return readl(phy->base + APB_PHY_START_ADDR + reg);  in hi3670_apb_phy_readl()
184 static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,  in hi3670_apb_phy_updatel()  argument
189 	regval = hi3670_apb_phy_readl(phy, reg);  in hi3670_apb_phy_updatel()
192 	hi3670_apb_phy_writel(phy, regval, reg);  in hi3670_apb_phy_updatel()
195 static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,  in kirin_apb_natural_phy_writel()  argument
198 	writel(val, phy->base + reg);  in kirin_apb_natural_phy_writel()
201 static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,  in kirin_apb_natural_phy_readl()  argument
204 	return readl(phy->base + reg);  in kirin_apb_natural_phy_readl()
207 static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)  in hi3670_pcie_phy_oe_enable()  argument
211 	regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);  in hi3670_pcie_phy_oe_enable()
217 	regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);  in hi3670_pcie_phy_oe_enable()
220 static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)  in hi3670_pcie_get_eyeparam()  argument
222 	struct device *dev = phy->dev;  in hi3670_pcie_get_eyeparam()
229 					 phy->eye_param, NUM_EYEPARAM);  in hi3670_pcie_get_eyeparam()
235 		phy->eye_param[i] = EYEPARAM_NOCFG;  in hi3670_pcie_get_eyeparam()
238 static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)  in hi3670_pcie_set_eyeparam()  argument
242 	val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);  in hi3670_pcie_set_eyeparam()
244 	if (phy->eye_param[1] != EYEPARAM_NOCFG) {  in hi3670_pcie_set_eyeparam()
246 		val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);  in hi3670_pcie_set_eyeparam()
249 	kirin_apb_natural_phy_writel(phy, val,  in hi3670_pcie_set_eyeparam()
252 	val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);  in hi3670_pcie_set_eyeparam()
254 	if (phy->eye_param[2] != EYEPARAM_NOCFG) {  in hi3670_pcie_set_eyeparam()
255 		val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);  in hi3670_pcie_set_eyeparam()
259 	if (phy->eye_param[3] != EYEPARAM_NOCFG) {  in hi3670_pcie_set_eyeparam()
260 		val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);  in hi3670_pcie_set_eyeparam()
264 	kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);  in hi3670_pcie_set_eyeparam()
266 	val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);  in hi3670_pcie_set_eyeparam()
267 	if (phy->eye_param[0] != EYEPARAM_NOCFG) {  in hi3670_pcie_set_eyeparam()
269 		val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);  in hi3670_pcie_set_eyeparam()
272 	kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);  in hi3670_pcie_set_eyeparam()
274 	val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);  in hi3670_pcie_set_eyeparam()
275 	if (phy->eye_param[4] != EYEPARAM_NOCFG) {  in hi3670_pcie_set_eyeparam()
277 		val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);  in hi3670_pcie_set_eyeparam()
280 	kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);  in hi3670_pcie_set_eyeparam()
283 static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)  in hi3670_pcie_natural_cfg()  argument
288 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,  in hi3670_pcie_natural_cfg()
291 	regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);  in hi3670_pcie_natural_cfg()
293 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);  in hi3670_pcie_natural_cfg()
296 	regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);  in hi3670_pcie_natural_cfg()
299 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);  in hi3670_pcie_natural_cfg()
302 	hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,  in hi3670_pcie_natural_cfg()
307 	hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,  in hi3670_pcie_natural_cfg()
311 static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)  in hi3670_pcie_pll_init()  argument
313 	hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,  in hi3670_pcie_pll_init()
316 	hi3670_apb_phy_updatel(phy,  in hi3670_pcie_pll_init()
321 	hi3670_apb_phy_updatel(phy,  in hi3670_pcie_pll_init()
325 	hi3670_apb_phy_updatel(phy,  in hi3670_pcie_pll_init()
335 	hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,  in hi3670_pcie_pll_init()
339 static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)  in hi3670_pcie_pll_ctrl()  argument
341 	struct device *dev = phy->dev;  in hi3670_pcie_pll_ctrl()
347 		hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,  in hi3670_pcie_pll_ctrl()
351 		val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);  in hi3670_pcie_pll_ctrl()
359 			val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);  in hi3670_pcie_pll_ctrl()
362 		hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,  in hi3670_pcie_pll_ctrl()
366 		hi3670_apb_phy_updatel(phy,  in hi3670_pcie_pll_ctrl()
371 		hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,  in hi3670_pcie_pll_ctrl()
379 static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)  in hi3670_pcie_hp_debounce_gt()  argument
383 		regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,  in hi3670_pcie_hp_debounce_gt()
387 		regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,  in hi3670_pcie_hp_debounce_gt()
391 static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)  in hi3670_pcie_phyref_gt()  argument
395 	regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);  in hi3670_pcie_phyref_gt()
402 	regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);  in hi3670_pcie_phyref_gt()
405 	regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);  in hi3670_pcie_phyref_gt()
408 static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)  in hi3670_pcie_oe_ctrl()  argument
412 	regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);  in hi3670_pcie_oe_ctrl()
431 	regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);  in hi3670_pcie_oe_ctrl()
434 static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)  in hi3670_pcie_ioref_gt()  argument
439 		regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,  in hi3670_pcie_ioref_gt()
442 		hi3670_pcie_oe_ctrl(phy, true);  in hi3670_pcie_ioref_gt()
445 		regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);  in hi3670_pcie_ioref_gt()
447 		regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);  in hi3670_pcie_ioref_gt()
450 		regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,  in hi3670_pcie_ioref_gt()
455 		regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);  in hi3670_pcie_ioref_gt()
457 		regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);  in hi3670_pcie_ioref_gt()
460 		regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,  in hi3670_pcie_ioref_gt()
463 		hi3670_pcie_oe_ctrl(phy, false);  in hi3670_pcie_ioref_gt()
467 static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)  in hi3670_pcie_allclk_ctrl()  argument
469 	struct device *dev = phy->dev;  in hi3670_pcie_allclk_ctrl()
476 	hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,  in hi3670_pcie_allclk_ctrl()
479 	hi3670_pcie_pll_init(phy);  in hi3670_pcie_allclk_ctrl()
481 	ret = hi3670_pcie_pll_ctrl(phy, true);  in hi3670_pcie_allclk_ctrl()
486 	hi3670_pcie_hp_debounce_gt(phy, true);  in hi3670_pcie_allclk_ctrl()
487 	hi3670_pcie_phyref_gt(phy, true);  in hi3670_pcie_allclk_ctrl()
488 	hi3670_pcie_ioref_gt(phy, true);  in hi3670_pcie_allclk_ctrl()
490 	ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);  in hi3670_pcie_allclk_ctrl()
499 	hi3670_pcie_ioref_gt(phy, false);  in hi3670_pcie_allclk_ctrl()
500 	hi3670_pcie_phyref_gt(phy, false);  in hi3670_pcie_allclk_ctrl()
501 	hi3670_pcie_hp_debounce_gt(phy, false);  in hi3670_pcie_allclk_ctrl()
503 	hi3670_pcie_pll_ctrl(phy, false);  in hi3670_pcie_allclk_ctrl()
508 static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)  in is_pipe_clk_stable()  argument
510 	struct device *dev = phy->dev;  in is_pipe_clk_stable()
515 	val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);  in is_pipe_clk_stable()
523 		val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);  in is_pipe_clk_stable()
529 static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)  in hi3670_pcie_noc_power()  argument
531 	struct device *dev = phy->dev;  in hi3670_pcie_noc_power()
542 	regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);  in hi3670_pcie_noc_power()
545 	regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);  in hi3670_pcie_noc_power()
553 		regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);  in hi3670_pcie_noc_power()
559 static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)  in hi3670_pcie_get_resources_from_pcie()  argument
562 	struct device *dev = phy->dev;  in hi3670_pcie_get_resources_from_pcie()
586 	phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");  in hi3670_pcie_get_resources_from_pcie()
587 	if (!phy->apb) {  in hi3670_pcie_get_resources_from_pcie()
595 static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)  in kirin_pcie_clk_ctrl()  argument
602 	ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);  in kirin_pcie_clk_ctrl()
606 	ret = clk_prepare_enable(phy->phy_ref_clk);  in kirin_pcie_clk_ctrl()
610 	ret = clk_prepare_enable(phy->apb_sys_clk);  in kirin_pcie_clk_ctrl()
614 	ret = clk_prepare_enable(phy->apb_phy_clk);  in kirin_pcie_clk_ctrl()
618 	ret = clk_prepare_enable(phy->aclk);  in kirin_pcie_clk_ctrl()
622 	ret = clk_prepare_enable(phy->aux_clk);  in kirin_pcie_clk_ctrl()
629 	clk_disable_unprepare(phy->aux_clk);  in kirin_pcie_clk_ctrl()
631 	clk_disable_unprepare(phy->aclk);  in kirin_pcie_clk_ctrl()
633 	clk_disable_unprepare(phy->apb_phy_clk);  in kirin_pcie_clk_ctrl()
635 	clk_disable_unprepare(phy->apb_sys_clk);  in kirin_pcie_clk_ctrl()
637 	clk_disable_unprepare(phy->phy_ref_clk);  in kirin_pcie_clk_ctrl()
642 static int hi3670_pcie_phy_init(struct phy *generic_phy)  in hi3670_pcie_phy_init()
644 	struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);  in hi3670_pcie_phy_init()  local
658 	ret = hi3670_pcie_get_resources_from_pcie(phy);  in hi3670_pcie_phy_init()
665 static int hi3670_pcie_phy_power_on(struct phy *generic_phy)  in hi3670_pcie_phy_power_on()
667 	struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);  in hi3670_pcie_phy_power_on()  local
671 	regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);  in hi3670_pcie_phy_power_on()
674 	hi3670_pcie_phy_oe_enable(phy, true);  in hi3670_pcie_phy_power_on()
676 	ret = kirin_pcie_clk_ctrl(phy, true);  in hi3670_pcie_phy_power_on()
680 	/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */  in hi3670_pcie_phy_power_on()
681 	regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);  in hi3670_pcie_phy_power_on()
682 	regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,  in hi3670_pcie_phy_power_on()
684 	regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,  in hi3670_pcie_phy_power_on()
687 	hi3670_pcie_natural_cfg(phy);  in hi3670_pcie_phy_power_on()
689 	ret = hi3670_pcie_allclk_ctrl(phy, true);  in hi3670_pcie_phy_power_on()
694 	hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,  in hi3670_pcie_phy_power_on()
698 	regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);  in hi3670_pcie_phy_power_on()
700 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);  in hi3670_pcie_phy_power_on()
703 	ret = is_pipe_clk_stable(phy);  in hi3670_pcie_phy_power_on()
707 	hi3670_pcie_set_eyeparam(phy);  in hi3670_pcie_phy_power_on()
709 	ret = hi3670_pcie_noc_power(phy, false);  in hi3670_pcie_phy_power_on()
716 	kirin_pcie_clk_ctrl(phy, false);  in hi3670_pcie_phy_power_on()
720 static int hi3670_pcie_phy_power_off(struct phy *generic_phy)  in hi3670_pcie_phy_power_off()
722 	struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);  in hi3670_pcie_phy_power_off()  local
724 	hi3670_pcie_phy_oe_enable(phy, false);  in hi3670_pcie_phy_power_off()
726 	hi3670_pcie_allclk_ctrl(phy, false);  in hi3670_pcie_phy_power_off()
729 	regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);  in hi3670_pcie_phy_power_off()
733 	 * kirin_pcie_clk_ctrl(phy, false);  in hi3670_pcie_phy_power_off()
750 static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,  in hi3670_pcie_phy_get_resources()  argument
756 	phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");  in hi3670_pcie_phy_get_resources()
757 	if (IS_ERR(phy->crgctrl))  in hi3670_pcie_phy_get_resources()
758 		return PTR_ERR(phy->crgctrl);  in hi3670_pcie_phy_get_resources()
760 	phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");  in hi3670_pcie_phy_get_resources()
761 	if (IS_ERR(phy->sysctrl))  in hi3670_pcie_phy_get_resources()
762 		return PTR_ERR(phy->sysctrl);  in hi3670_pcie_phy_get_resources()
764 	phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");  in hi3670_pcie_phy_get_resources()
765 	if (IS_ERR(phy->pmctrl))  in hi3670_pcie_phy_get_resources()
766 		return PTR_ERR(phy->pmctrl);  in hi3670_pcie_phy_get_resources()
769 	phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");  in hi3670_pcie_phy_get_resources()
770 	if (IS_ERR(phy->phy_ref_clk))  in hi3670_pcie_phy_get_resources()
771 		return PTR_ERR(phy->phy_ref_clk);  in hi3670_pcie_phy_get_resources()
773 	phy->aux_clk = devm_clk_get(dev, "aux");  in hi3670_pcie_phy_get_resources()
774 	if (IS_ERR(phy->aux_clk))  in hi3670_pcie_phy_get_resources()
775 		return PTR_ERR(phy->aux_clk);  in hi3670_pcie_phy_get_resources()
777 	phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");  in hi3670_pcie_phy_get_resources()
778 	if (IS_ERR(phy->apb_phy_clk))  in hi3670_pcie_phy_get_resources()
779 		return PTR_ERR(phy->apb_phy_clk);  in hi3670_pcie_phy_get_resources()
781 	phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");  in hi3670_pcie_phy_get_resources()
782 	if (IS_ERR(phy->apb_sys_clk))  in hi3670_pcie_phy_get_resources()
783 		return PTR_ERR(phy->apb_sys_clk);  in hi3670_pcie_phy_get_resources()
785 	phy->aclk = devm_clk_get(dev, "aclk");  in hi3670_pcie_phy_get_resources()
786 	if (IS_ERR(phy->aclk))  in hi3670_pcie_phy_get_resources()
787 		return PTR_ERR(phy->aclk);  in hi3670_pcie_phy_get_resources()
790 	phy->base = devm_platform_ioremap_resource(pdev, 0);  in hi3670_pcie_phy_get_resources()
791 	if (IS_ERR(phy->base))  in hi3670_pcie_phy_get_resources()
792 		return PTR_ERR(phy->base);  in hi3670_pcie_phy_get_resources()
794 	hi3670_pcie_get_eyeparam(phy);  in hi3670_pcie_phy_get_resources()
803 	struct hi3670_pcie_phy *phy;  in hi3670_pcie_phy_probe()  local
804 	struct phy *generic_phy;  in hi3670_pcie_phy_probe()
807 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);  in hi3670_pcie_phy_probe()
808 	if (!phy)  in hi3670_pcie_phy_probe()
811 	phy->dev = dev;  in hi3670_pcie_phy_probe()
813 	ret = hi3670_pcie_phy_get_resources(phy, pdev);  in hi3670_pcie_phy_probe()
819 		dev_err(dev, "failed to create PHY\n");  in hi3670_pcie_phy_probe()
823 	phy_set_drvdata(generic_phy, phy);  in hi3670_pcie_phy_probe()
831 		.compatible = "hisilicon,hi970-pcie-phy",
847 MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");