Lines Matching +full:apb +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
159 void __iomem *base; member
160 struct regmap *apb; member
176 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
181 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
198 writel(val, phy->base + reg); in kirin_apb_natural_phy_writel()
204 return readl(phy->base + reg); in kirin_apb_natural_phy_readl()
211 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); in hi3670_pcie_phy_oe_enable()
217 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); in hi3670_pcie_phy_oe_enable()
222 struct device *dev = phy->dev; in hi3670_pcie_get_eyeparam()
226 np = dev->of_node; in hi3670_pcie_get_eyeparam()
228 ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param", in hi3670_pcie_get_eyeparam()
229 phy->eye_param, NUM_EYEPARAM); in hi3670_pcie_get_eyeparam()
235 phy->eye_param[i] = EYEPARAM_NOCFG; in hi3670_pcie_get_eyeparam()
244 if (phy->eye_param[1] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
246 val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]); in hi3670_pcie_set_eyeparam()
254 if (phy->eye_param[2] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
255 val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]); in hi3670_pcie_set_eyeparam()
259 if (phy->eye_param[3] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
260 val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]); in hi3670_pcie_set_eyeparam()
267 if (phy->eye_param[0] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
269 val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]); in hi3670_pcie_set_eyeparam()
275 if (phy->eye_param[4] != EYEPARAM_NOCFG) { in hi3670_pcie_set_eyeparam()
277 val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]); in hi3670_pcie_set_eyeparam()
288 regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR, in hi3670_pcie_natural_cfg()
291 regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val); in hi3670_pcie_natural_cfg()
293 regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val); in hi3670_pcie_natural_cfg()
296 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val); in hi3670_pcie_natural_cfg()
299 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val); in hi3670_pcie_natural_cfg()
341 struct device *dev = phy->dev; in hi3670_pcie_pll_ctrl()
355 return -EINVAL; in hi3670_pcie_pll_ctrl()
357 time--; in hi3670_pcie_pll_ctrl()
383 regmap_write(phy->crgctrl, CRGPERIPH_PEREN12, in hi3670_pcie_hp_debounce_gt()
387 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, in hi3670_pcie_hp_debounce_gt()
395 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_phyref_gt()
402 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_phyref_gt()
405 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE); in hi3670_pcie_phyref_gt()
412 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_oe_ctrl()
431 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_oe_ctrl()
439 regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR, in hi3670_pcie_ioref_gt()
445 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_ioref_gt()
447 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_ioref_gt()
450 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, in hi3670_pcie_ioref_gt()
455 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); in hi3670_pcie_ioref_gt()
457 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); in hi3670_pcie_ioref_gt()
460 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, in hi3670_pcie_ioref_gt()
469 struct device *dev = phy->dev; in hi3670_pcie_allclk_ctrl()
484 return -EINVAL; in hi3670_pcie_allclk_ctrl()
490 ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ); in hi3670_pcie_allclk_ctrl()
510 struct device *dev = phy->dev; in is_pipe_clk_stable()
522 time--; in is_pipe_clk_stable()
531 struct device *dev = phy->dev; in hi3670_pcie_noc_power()
542 regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val); in hi3670_pcie_noc_power()
545 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val); in hi3670_pcie_noc_power()
549 dev_err(dev, "Failed to reverse noc power-status\n"); in hi3670_pcie_noc_power()
550 return -EINVAL; in hi3670_pcie_noc_power()
552 time--; in hi3670_pcie_noc_power()
553 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val); in hi3670_pcie_noc_power()
562 struct device *dev = phy->dev; in hi3670_pcie_get_resources_from_pcie()
565 pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); in hi3670_pcie_get_resources_from_pcie()
568 dev->parent->of_node->full_name); in hi3670_pcie_get_resources_from_pcie()
569 return -ENODEV; in hi3670_pcie_get_resources_from_pcie()
575 return -ENODEV; in hi3670_pcie_get_resources_from_pcie()
579 * We might just use NULL instead of the APB name, as the in hi3670_pcie_get_resources_from_pcie()
580 * pcie-kirin currently registers directly just one regmap (although in hi3670_pcie_get_resources_from_pcie()
586 phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb"); in hi3670_pcie_get_resources_from_pcie()
587 if (!phy->apb) { in hi3670_pcie_get_resources_from_pcie()
588 dev_err(dev, "Failed to get APB regmap\n"); in hi3670_pcie_get_resources_from_pcie()
589 return -ENODEV; in hi3670_pcie_get_resources_from_pcie()
602 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); in kirin_pcie_clk_ctrl()
606 ret = clk_prepare_enable(phy->phy_ref_clk); in kirin_pcie_clk_ctrl()
610 ret = clk_prepare_enable(phy->apb_sys_clk); in kirin_pcie_clk_ctrl()
614 ret = clk_prepare_enable(phy->apb_phy_clk); in kirin_pcie_clk_ctrl()
618 ret = clk_prepare_enable(phy->aclk); in kirin_pcie_clk_ctrl()
622 ret = clk_prepare_enable(phy->aux_clk); in kirin_pcie_clk_ctrl()
629 clk_disable_unprepare(phy->aux_clk); in kirin_pcie_clk_ctrl()
631 clk_disable_unprepare(phy->aclk); in kirin_pcie_clk_ctrl()
633 clk_disable_unprepare(phy->apb_phy_clk); in kirin_pcie_clk_ctrl()
635 clk_disable_unprepare(phy->apb_sys_clk); in kirin_pcie_clk_ctrl()
637 clk_disable_unprepare(phy->phy_ref_clk); in kirin_pcie_clk_ctrl()
649 * access the reset-gpios and the APB registers, both from the in hi3670_pcie_phy_init()
650 * pcie-kirin driver. in hi3670_pcie_phy_init()
652 * The APB is obtained via the pcie driver's regmap in hi3670_pcie_phy_init()
654 * power_on sequence, as the code inside pcie-kirin needs to in hi3670_pcie_phy_init()
655 * be already probed, as it needs to register the APB regmap. in hi3670_pcie_phy_init()
671 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); in hi3670_pcie_phy_power_on()
681 regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); in hi3670_pcie_phy_power_on()
682 regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET, in hi3670_pcie_phy_power_on()
684 regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET, in hi3670_pcie_phy_power_on()
698 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val); in hi3670_pcie_phy_power_on()
700 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val); in hi3670_pcie_phy_power_on()
729 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0); in hi3670_pcie_phy_power_off()
735 * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off in hi3670_pcie_phy_power_off()
737 * While clk-hi3670 is not fixed, we cannot risk disabling clocks here. in hi3670_pcie_phy_power_off()
753 struct device *dev = &pdev->dev; in hi3670_pcie_phy_get_resources()
756 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); in hi3670_pcie_phy_get_resources()
757 if (IS_ERR(phy->crgctrl)) in hi3670_pcie_phy_get_resources()
758 return PTR_ERR(phy->crgctrl); in hi3670_pcie_phy_get_resources()
760 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl"); in hi3670_pcie_phy_get_resources()
761 if (IS_ERR(phy->sysctrl)) in hi3670_pcie_phy_get_resources()
762 return PTR_ERR(phy->sysctrl); in hi3670_pcie_phy_get_resources()
764 phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl"); in hi3670_pcie_phy_get_resources()
765 if (IS_ERR(phy->pmctrl)) in hi3670_pcie_phy_get_resources()
766 return PTR_ERR(phy->pmctrl); in hi3670_pcie_phy_get_resources()
769 phy->phy_ref_clk = devm_clk_get(dev, "phy_ref"); in hi3670_pcie_phy_get_resources()
770 if (IS_ERR(phy->phy_ref_clk)) in hi3670_pcie_phy_get_resources()
771 return PTR_ERR(phy->phy_ref_clk); in hi3670_pcie_phy_get_resources()
773 phy->aux_clk = devm_clk_get(dev, "aux"); in hi3670_pcie_phy_get_resources()
774 if (IS_ERR(phy->aux_clk)) in hi3670_pcie_phy_get_resources()
775 return PTR_ERR(phy->aux_clk); in hi3670_pcie_phy_get_resources()
777 phy->apb_phy_clk = devm_clk_get(dev, "apb_phy"); in hi3670_pcie_phy_get_resources()
778 if (IS_ERR(phy->apb_phy_clk)) in hi3670_pcie_phy_get_resources()
779 return PTR_ERR(phy->apb_phy_clk); in hi3670_pcie_phy_get_resources()
781 phy->apb_sys_clk = devm_clk_get(dev, "apb_sys"); in hi3670_pcie_phy_get_resources()
782 if (IS_ERR(phy->apb_sys_clk)) in hi3670_pcie_phy_get_resources()
783 return PTR_ERR(phy->apb_sys_clk); in hi3670_pcie_phy_get_resources()
785 phy->aclk = devm_clk_get(dev, "aclk"); in hi3670_pcie_phy_get_resources()
786 if (IS_ERR(phy->aclk)) in hi3670_pcie_phy_get_resources()
787 return PTR_ERR(phy->aclk); in hi3670_pcie_phy_get_resources()
790 phy->base = devm_platform_ioremap_resource(pdev, 0); in hi3670_pcie_phy_get_resources()
791 if (IS_ERR(phy->base)) in hi3670_pcie_phy_get_resources()
792 return PTR_ERR(phy->base); in hi3670_pcie_phy_get_resources()
802 struct device *dev = &pdev->dev; in hi3670_pcie_phy_probe()
809 return -ENOMEM; in hi3670_pcie_phy_probe()
811 phy->dev = dev; in hi3670_pcie_phy_probe()
817 generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops); in hi3670_pcie_phy_probe()
831 .compatible = "hisilicon,hi970-pcie-phy",