Lines Matching full:lane
96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
129 lane->phy_off = 0; in imx_hsio_init()
132 if (lane->idx == 0) in imx_hsio_init()
133 lane->clks[i].id = lan0_pcie_clks[i]; in imx_hsio_init()
135 lane->clks[i].id = lan1_pciea_clks[i]; in imx_hsio_init()
138 if (lane->idx == 0) { /* i.MX8QXP */ in imx_hsio_init()
139 lane->ctrl_off = 0; in imx_hsio_init()
140 lane->phy_off = 0; in imx_hsio_init()
143 * On i.MX8QM, only second or third lane can be in imx_hsio_init()
146 lane->ctrl_off = SZ_64K; in imx_hsio_init()
147 if (lane->idx == 1) in imx_hsio_init()
148 lane->phy_off = 0; in imx_hsio_init()
149 else /* the third lane is bound to PCIEB */ in imx_hsio_init()
150 lane->phy_off = SZ_64K; in imx_hsio_init()
154 if (lane->idx == 1) in imx_hsio_init()
155 lane->clks[i].id = lan1_pcieb_clks[i]; in imx_hsio_init()
156 else if (lane->idx == 2) in imx_hsio_init()
157 lane->clks[i].id = lan2_pcieb_clks[i]; in imx_hsio_init()
159 lane->clks[i].id = lan0_pcie_clks[i]; in imx_hsio_init()
164 /* On i.MX8QM, only the third lane can be bound to SATA */ in imx_hsio_init()
165 lane->phy_mode = PHY_MODE_SATA; in imx_hsio_init()
166 lane->ctrl_off = SZ_128K; in imx_hsio_init()
167 lane->phy_off = SZ_64K; in imx_hsio_init()
170 lane->clks[i].id = lan2_sata_clks[i]; in imx_hsio_init()
177 ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks); in imx_hsio_init()
180 ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks); in imx_hsio_init()
191 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_exit() local
193 clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks); in imx_hsio_exit()
200 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_pcie_phy_resets() local
201 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_pcie_phy_resets()
203 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
205 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
207 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
209 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
211 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
213 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_pcie_phy_resets()
216 if (lane->idx == 1) { in imx_hsio_pcie_phy_resets()
217 regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, in imx_hsio_pcie_phy_resets()
219 regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, in imx_hsio_pcie_phy_resets()
222 regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, in imx_hsio_pcie_phy_resets()
224 regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, in imx_hsio_pcie_phy_resets()
231 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_sata_phy_resets() local
232 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_sata_phy_resets()
235 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_phy_resets()
237 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_phy_resets()
241 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N); in imx_hsio_sata_phy_resets()
243 regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_phy_resets()
245 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N); in imx_hsio_sata_phy_resets()
251 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_configure_clk_pad() local
252 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_configure_clk_pad()
273 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_pre_set() local
274 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_pre_set()
292 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_pcie_power_on() local
293 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_pcie_power_on()
298 clk_disable_unprepare(lane->clks[0].clk); in imx_hsio_pcie_power_on()
300 ret = clk_prepare_enable(lane->clks[0].clk); in imx_hsio_pcie_power_on()
306 addr = lane->ctrl_off + HSIO_PCIE_STS0; in imx_hsio_pcie_power_on()
321 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_sata_power_on() local
322 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_sata_power_on()
324 regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0); in imx_hsio_sata_power_on()
325 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_power_on()
327 regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_sata_power_on()
349 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_power_on() local
350 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_power_on()
358 if (lane->phy_mode == PHY_MODE_PCIE) in imx_hsio_power_on()
366 if (lane->idx == 1) in imx_hsio_power_on()
375 ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0, in imx_hsio_power_on()
380 dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx); in imx_hsio_power_on()
383 dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx); in imx_hsio_power_on()
390 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_power_off() local
391 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_power_off()
401 if (lane->phy_mode == PHY_MODE_PCIE) { in imx_hsio_power_off()
403 lane->ctrl_off + HSIO_CTRL2, in imx_hsio_power_off()
406 lane->ctrl_off + HSIO_CTRL2, in imx_hsio_power_off()
409 lane->ctrl_off + HSIO_CTRL2, in imx_hsio_power_off()
413 lane->ctrl_off + HSIO_CTRL0, in imx_hsio_power_off()
416 lane->ctrl_off + HSIO_CTRL0, in imx_hsio_power_off()
419 lane->ctrl_off + HSIO_CTRL0, in imx_hsio_power_off()
423 if (lane->idx == 1) { in imx_hsio_power_off()
425 lane->phy_off + HSIO_CTRL0, in imx_hsio_power_off()
428 lane->phy_off + HSIO_CTRL0, in imx_hsio_power_off()
437 lane->phy_off + HSIO_CTRL0, in imx_hsio_power_off()
440 lane->phy_off + HSIO_CTRL0, in imx_hsio_power_off()
453 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_set_mode() local
454 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_set_mode()
456 if (lane->phy_mode != mode) in imx_hsio_set_mode()
461 regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0, in imx_hsio_set_mode()
475 regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, in imx_hsio_set_mode()
483 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_set_speed() local
484 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_set_speed()
486 regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2, in imx_hsio_set_speed()
527 priv->lane[idx].idx = idx; in imx_hsio_xlate()
528 priv->lane[idx].phy_type = phy_type; in imx_hsio_xlate()
529 priv->lane[idx].ctrl_index = ctrl_index; in imx_hsio_xlate()
531 return priv->lane[idx].phy; in imx_hsio_xlate()
580 struct imx_hsio_lane *lane = &priv->lane[i]; in imx_hsio_probe() local
587 lane->priv = priv; in imx_hsio_probe()
588 lane->phy = phy; in imx_hsio_probe()
589 lane->idx = i; in imx_hsio_probe()
590 phy_set_drvdata(phy, lane); in imx_hsio_probe()