Lines Matching +full:0 +full:x3220
30 #define SIERRA_COMMON_CDB_OFFSET 0x0
31 #define SIERRA_MACRO_ID_REG 0x0
32 #define SIERRA_CMN_PLLLC_GEN_PREG 0x42
33 #define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG 0x43
34 #define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG 0x45
35 #define SIERRA_CMN_PLLLC_INIT_PREG 0x46
36 #define SIERRA_CMN_PLLLC_ITERTMR_PREG 0x47
37 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48
38 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
39 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
40 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B
41 #define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG 0x4C
42 #define SIERRA_CMN_PLLLC_CLK1_PREG 0x4D
43 #define SIERRA_CMN_PLLLC_CLK0_PREG 0x4E
44 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
45 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
46 #define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51
47 #define SIERRA_CMN_PLLLC_SS_PREG 0x52
48 #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53
49 #define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54
50 #define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG 0x5D
51 #define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG 0x5E
52 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
53 #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
54 #define SIERRA_SDOSCCAL_CLK_CNT_PREG 0x6E
55 #define SIERRA_CMN_REFRCV_PREG 0x98
56 #define SIERRA_CMN_RESCAL_CTRLA_PREG 0xA0
57 #define SIERRA_CMN_REFRCV1_PREG 0xB8
58 #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
59 #define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3
60 #define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5
61 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
62 #define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE
63 #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
64 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
67 ((0x4000 << (block_offset)) + \
70 #define SIERRA_DET_STANDEC_A_PREG 0x000
71 #define SIERRA_DET_STANDEC_B_PREG 0x001
72 #define SIERRA_DET_STANDEC_C_PREG 0x002
73 #define SIERRA_DET_STANDEC_D_PREG 0x003
74 #define SIERRA_DET_STANDEC_E_PREG 0x004
75 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
76 #define SIERRA_PSM_A0IN_TMR_PREG 0x009
77 #define SIERRA_PSM_A3IN_TMR_PREG 0x00C
78 #define SIERRA_PSM_DIAG_PREG 0x015
79 #define SIERRA_PSC_LN_A3_PREG 0x023
80 #define SIERRA_PSC_LN_A4_PREG 0x024
81 #define SIERRA_PSC_LN_IDLE_PREG 0x026
82 #define SIERRA_PSC_TX_A0_PREG 0x028
83 #define SIERRA_PSC_TX_A1_PREG 0x029
84 #define SIERRA_PSC_TX_A2_PREG 0x02A
85 #define SIERRA_PSC_TX_A3_PREG 0x02B
86 #define SIERRA_PSC_RX_A0_PREG 0x030
87 #define SIERRA_PSC_RX_A1_PREG 0x031
88 #define SIERRA_PSC_RX_A2_PREG 0x032
89 #define SIERRA_PSC_RX_A3_PREG 0x033
90 #define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039
91 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
92 #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
93 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
94 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F
95 #define SIERRA_PLLCTRL_STATUS_PREG 0x044
96 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
97 #define SIERRA_DFE_BIASTRIM_PREG 0x04C
98 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
99 #define SIERRA_DRVCTRL_BOOST_PREG 0x06F
100 #define SIERRA_LANE_TX_RECEIVER_DETECT_PREG 0x071
101 #define SIERRA_TX_RCVDET_OVRD_PREG 0x072
102 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
103 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
104 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
105 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
106 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
107 #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C
108 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E
109 #define SIERRA_RX_CTLE_CAL_PREG 0x08F
110 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091
111 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092
112 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093
113 #define SIERRA_CREQ_SPARE_PREG 0x096
114 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097
115 #define SIERRA_CTLELUT_CTRL_PREG 0x098
116 #define SIERRA_DEQ_BLK_TAU_CTRL1_PREG 0x0AC
117 #define SIERRA_DEQ_BLK_TAU_CTRL4_PREG 0x0AF
118 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0
119 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1
120 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4
121 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8
122 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9
123 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD
124 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE
125 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0
126 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8
127 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0
128 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1
129 #define SIERRA_DEQ_GLUT0 0x0E8
130 #define SIERRA_DEQ_GLUT1 0x0E9
131 #define SIERRA_DEQ_GLUT2 0x0EA
132 #define SIERRA_DEQ_GLUT3 0x0EB
133 #define SIERRA_DEQ_GLUT4 0x0EC
134 #define SIERRA_DEQ_GLUT5 0x0ED
135 #define SIERRA_DEQ_GLUT6 0x0EE
136 #define SIERRA_DEQ_GLUT7 0x0EF
137 #define SIERRA_DEQ_GLUT8 0x0F0
138 #define SIERRA_DEQ_GLUT9 0x0F1
139 #define SIERRA_DEQ_GLUT10 0x0F2
140 #define SIERRA_DEQ_GLUT11 0x0F3
141 #define SIERRA_DEQ_GLUT12 0x0F4
142 #define SIERRA_DEQ_GLUT13 0x0F5
143 #define SIERRA_DEQ_GLUT14 0x0F6
144 #define SIERRA_DEQ_GLUT15 0x0F7
145 #define SIERRA_DEQ_GLUT16 0x0F8
146 #define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG 0x0F9
147 #define SIERRA_TAU_EN_CEPH2TO0_PREG 0x0FB
148 #define SIERRA_TAU_EN_CEPH5TO3_PREG 0x0FC
149 #define SIERRA_DEQ_ALUT0 0x108
150 #define SIERRA_DEQ_ALUT1 0x109
151 #define SIERRA_DEQ_ALUT2 0x10A
152 #define SIERRA_DEQ_ALUT3 0x10B
153 #define SIERRA_DEQ_ALUT4 0x10C
154 #define SIERRA_DEQ_ALUT5 0x10D
155 #define SIERRA_DEQ_ALUT6 0x10E
156 #define SIERRA_DEQ_ALUT7 0x10F
157 #define SIERRA_DEQ_ALUT8 0x110
158 #define SIERRA_DEQ_ALUT9 0x111
159 #define SIERRA_DEQ_ALUT10 0x112
160 #define SIERRA_DEQ_ALUT11 0x113
161 #define SIERRA_DEQ_ALUT12 0x114
162 #define SIERRA_DEQ_ALUT13 0x115
163 #define SIERRA_OEPH_EN_CTRL_PREG 0x124
164 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128
165 #define SIERRA_DEQ_DFETAP0 0x129
166 #define SIERRA_DEQ_DFETAP1 0x12B
167 #define SIERRA_DEQ_DFETAP2 0x12D
168 #define SIERRA_DEQ_DFETAP3 0x12F
169 #define SIERRA_DEQ_DFETAP4 0x131
170 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
171 #define SIERRA_DEQ_PRECUR_PREG 0x138
172 #define SIERRA_DEQ_POSTCUR_PREG 0x140
173 #define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142
174 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
175 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
176 #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
177 #define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG 0x158
178 #define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG 0x159
179 #define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x15C
180 #define SIERRA_DEQ_PICTRL_PREG 0x161
181 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
182 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
183 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
184 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
185 #define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E
186 #define SIERRA_CPI_TRIM_PREG 0x17F
187 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
188 #define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG 0x184
189 #define SIERRA_EPI_CTRL_PREG 0x187
190 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188
191 #define SIERRA_LFPSFILT_NS_PREG 0x18A
192 #define SIERRA_LFPSFILT_RD_PREG 0x18B
193 #define SIERRA_LFPSFILT_MP_PREG 0x18C
194 #define SIERRA_SIGDET_SUPPORT_PREG 0x190
195 #define SIERRA_SDFILT_H2L_A_PREG 0x191
196 #define SIERRA_SDFILT_L2H_PREG 0x193
197 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E
198 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F
199 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0
200 #define SIERRA_LN_SPARE_REG_PREG 0x1B0
201 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
202 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
206 (0xc000 << (block_offset))
207 #define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
208 #define SIERRA_PHY_PLL_CFG 0xe
212 ((0xD000 << (block_offset)) + \
215 #define SIERRA_PHY_ISO_LINK_CTRL 0xB
219 (0xE000 << (block_offset))
220 #define SIERRA_PHY_PMA_CMN_CTRL 0x000
224 ((0xF000 << (block_offset)) + \
227 #define SIERRA_PHY_PMA_XCVR_CTRL 0x000
229 #define SIERRA_MACRO_ID 0x00007364
245 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
249 REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
251 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
255 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);
280 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
285 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
315 [CMN_PLLLC] = { 0, 1 },
316 [CMN_PLLLC1] = { 1, 0 },
418 return 0; in cdns_regmap_write()
427 return 0; in cdns_regmap_read()
440 SIERRA_LANE_CDB_REGMAP_CONF("0"),
484 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
520 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"),
555 return 0; in cdns_sierra_phy_init()
566 for (i = 0; i < num_regs; i++) in cdns_sierra_phy_init()
575 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
577 for (j = 0; j < num_regs; j++) in cdns_sierra_phy_init()
588 for (i = 0; i < num_regs; i++) in cdns_sierra_phy_init()
597 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
599 for (j = 0; j < num_regs; j++) in cdns_sierra_phy_init()
604 return 0; in cdns_sierra_phy_init()
642 * PHY_PMA_CMN_CTRL[0] == 1 in cdns_sierra_phy_on()
653 if (ret < 0) in cdns_sierra_phy_on()
672 return 0; in cdns_sierra_phy_reset()
687 return 0; in cdns_sierra_noop_phy_on()
707 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val); in cdns_sierra_pll_mux_get_parent()
713 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val); in cdns_sierra_pll_mux_get_parent()
727 ret = regmap_field_write(plllc1en_field, 0); in cdns_sierra_pll_mux_set_parent()
728 ret |= regmap_field_write(termen_field, 0); in cdns_sierra_pll_mux_set_parent()
790 return 0; in cdns_sierra_pll_mux_register()
799 int ret = 0, i, clk_index; in cdns_sierra_phy_register_pll_mux()
802 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { in cdns_sierra_phy_register_pll_mux()
815 return 0; in cdns_sierra_phy_register_pll_mux()
822 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1); in cdns_sierra_derived_refclk_enable()
825 regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E); in cdns_sierra_derived_refclk_enable()
827 return 0; in cdns_sierra_derived_refclk_enable()
834 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0); in cdns_sierra_derived_refclk_disable()
873 init->flags = 0; in cdns_sierra_derived_refclk_register()
900 return 0; in cdns_sierra_derived_refclk_register()
972 return 0; in cdns_sierra_get_optional()
1008 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { in cdns_regfield_init()
1050 for (i = 0; i < SIERRA_MAX_LANES; i++) { in cdns_regfield_init()
1060 for (i = 0; i < SIERRA_MAX_LANES; i++) { in cdns_regfield_init()
1070 return 0; in cdns_regfield_init()
1082 for (i = 0; i < SIERRA_MAX_LANES; i++) { in cdns_regmap_init_blocks()
1113 for (i = 0; i < SIERRA_MAX_LANES; i++) { in cdns_regmap_init_blocks()
1135 for (i = 0; i < SIERRA_MAX_LANES; i++) { in cdns_regmap_init_blocks()
1148 return 0; in cdns_regmap_init_blocks()
1173 return 0; in cdns_sierra_phy_get_clocks()
1193 return 0; in cdns_sierra_phy_clk()
1208 return 0; in cdns_sierra_phy_enable_clocks()
1243 return 0; in cdns_sierra_phy_get_resets()
1267 regmap_field_write(sp->phy_pll_cfg_1, 0x1); in cdns_sierra_phy_configure_multilink()
1269 phy_t1 = sp->phys[0].phy_type; in cdns_sierra_phy_configure_multilink()
1292 for (node = 0; node < sp->nsubnodes; node++) { in cdns_sierra_phy_configure_multilink()
1311 for (i = 0; i < num_regs; i++) in cdns_sierra_phy_configure_multilink()
1320 for (i = 0; i < num_lanes; i++) { in cdns_sierra_phy_configure_multilink()
1322 for (j = 0; j < num_regs; j++) in cdns_sierra_phy_configure_multilink()
1333 for (i = 0; i < num_regs; i++) in cdns_sierra_phy_configure_multilink()
1342 for (i = 0; i < num_lanes; i++) { in cdns_sierra_phy_configure_multilink()
1344 for (j = 0; j < num_regs; j++) in cdns_sierra_phy_configure_multilink()
1358 return 0; in cdns_sierra_phy_configure_multilink()
1368 int ret, node = 0; in cdns_sierra_phy_probe()
1372 if (of_get_child_count(dn) == 0) in cdns_sierra_phy_probe()
1389 base = devm_platform_ioremap_resource(pdev, 0); in cdns_sierra_phy_probe()
1507 return 0; in cdns_sierra_phy_probe()
1510 while (--node >= 0) in cdns_sierra_phy_probe()
1536 for (i = 0; i < phy->nsubnodes; i++) { in cdns_sierra_phy_remove()
1546 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
1556 {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
1557 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1558 {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},
1559 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1560 {0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1564 {0x688E, SIERRA_DET_STANDEC_D_PREG},
1565 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1566 {0x0FFE, SIERRA_PSC_RX_A0_PREG},
1567 {0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
1568 {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
1569 {0x0003, SIERRA_PLLCTRL_GEN_A_PREG},
1570 {0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
1571 {0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG },
1572 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1573 {0x9702, SIERRA_DRVCTRL_BOOST_PREG},
1574 {0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1575 {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1576 {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
1577 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1578 {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1579 {0x0186, SIERRA_DEQ_GLUT0},
1580 {0x0186, SIERRA_DEQ_GLUT1},
1581 {0x0186, SIERRA_DEQ_GLUT2},
1582 {0x0186, SIERRA_DEQ_GLUT3},
1583 {0x0186, SIERRA_DEQ_GLUT4},
1584 {0x0861, SIERRA_DEQ_ALUT0},
1585 {0x07E0, SIERRA_DEQ_ALUT1},
1586 {0x079E, SIERRA_DEQ_ALUT2},
1587 {0x071D, SIERRA_DEQ_ALUT3},
1588 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
1589 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1590 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1591 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
1592 {0x0033, SIERRA_DEQ_PICTRL_PREG},
1593 {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1594 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
1595 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
1596 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
1611 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
1621 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1622 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1623 {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1627 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1628 {0x0252, SIERRA_DET_STANDEC_E_PREG},
1629 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1630 {0x0FFE, SIERRA_PSC_RX_A0_PREG},
1631 {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
1632 {0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
1633 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
1634 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1635 {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1636 {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1637 {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
1638 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1639 {0x8422, SIERRA_CTLELUT_CTRL_PREG},
1640 {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},
1641 {0x4111, SIERRA_DFE_SMP_RATESEL_PREG},
1642 {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1643 {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},
1644 {0x0186, SIERRA_DEQ_GLUT0},
1645 {0x0186, SIERRA_DEQ_GLUT1},
1646 {0x0186, SIERRA_DEQ_GLUT2},
1647 {0x0186, SIERRA_DEQ_GLUT3},
1648 {0x0186, SIERRA_DEQ_GLUT4},
1649 {0x0861, SIERRA_DEQ_ALUT0},
1650 {0x07E0, SIERRA_DEQ_ALUT1},
1651 {0x079E, SIERRA_DEQ_ALUT2},
1652 {0x071D, SIERRA_DEQ_ALUT3},
1653 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
1654 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1655 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1656 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
1657 {0x0033, SIERRA_DEQ_PICTRL_PREG},
1658 {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
1659 {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1660 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
1661 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
1662 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
1677 {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
1687 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1688 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1689 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1690 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
1698 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1699 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1700 {0x0004, SIERRA_PSC_LN_A3_PREG},
1701 {0x0004, SIERRA_PSC_LN_A4_PREG},
1702 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1703 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1704 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1705 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1706 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1707 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1708 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1709 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1710 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1711 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1712 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1713 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1714 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1715 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1716 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1717 {0x0041, SIERRA_DEQ_GLUT0},
1718 {0x0082, SIERRA_DEQ_GLUT1},
1719 {0x00C3, SIERRA_DEQ_GLUT2},
1720 {0x0145, SIERRA_DEQ_GLUT3},
1721 {0x0186, SIERRA_DEQ_GLUT4},
1722 {0x09E7, SIERRA_DEQ_ALUT0},
1723 {0x09A6, SIERRA_DEQ_ALUT1},
1724 {0x0965, SIERRA_DEQ_ALUT2},
1725 {0x08E3, SIERRA_DEQ_ALUT3},
1726 {0x00FA, SIERRA_DEQ_DFETAP0},
1727 {0x00FA, SIERRA_DEQ_DFETAP1},
1728 {0x00FA, SIERRA_DEQ_DFETAP2},
1729 {0x00FA, SIERRA_DEQ_DFETAP3},
1730 {0x00FA, SIERRA_DEQ_DFETAP4},
1731 {0x000F, SIERRA_DEQ_PRECUR_PREG},
1732 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1733 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1734 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1735 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1736 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1737 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1738 {0x002B, SIERRA_CPI_TRIM_PREG},
1739 {0x0003, SIERRA_EPI_CTRL_PREG},
1740 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1741 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1742 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1743 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1762 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1763 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1764 {0x0004, SIERRA_PSC_LN_A3_PREG},
1765 {0x0004, SIERRA_PSC_LN_A4_PREG},
1766 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1767 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1768 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1769 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1770 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1771 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1772 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1773 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1774 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1775 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1776 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1777 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1778 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1779 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1780 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1781 {0x0041, SIERRA_DEQ_GLUT0},
1782 {0x0082, SIERRA_DEQ_GLUT1},
1783 {0x00C3, SIERRA_DEQ_GLUT2},
1784 {0x0145, SIERRA_DEQ_GLUT3},
1785 {0x0186, SIERRA_DEQ_GLUT4},
1786 {0x09E7, SIERRA_DEQ_ALUT0},
1787 {0x09A6, SIERRA_DEQ_ALUT1},
1788 {0x0965, SIERRA_DEQ_ALUT2},
1789 {0x08E3, SIERRA_DEQ_ALUT3},
1790 {0x00FA, SIERRA_DEQ_DFETAP0},
1791 {0x00FA, SIERRA_DEQ_DFETAP1},
1792 {0x00FA, SIERRA_DEQ_DFETAP2},
1793 {0x00FA, SIERRA_DEQ_DFETAP3},
1794 {0x00FA, SIERRA_DEQ_DFETAP4},
1795 {0x000F, SIERRA_DEQ_PRECUR_PREG},
1796 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1797 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1798 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1799 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1800 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1801 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1802 {0x002B, SIERRA_CPI_TRIM_PREG},
1803 {0x0003, SIERRA_EPI_CTRL_PREG},
1804 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1805 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1806 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1807 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
1808 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
1818 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
1819 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1820 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1821 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1822 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1823 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
1824 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
1825 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
1826 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
1827 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
1828 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
1836 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1837 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1838 {0x0004, SIERRA_PSC_LN_A3_PREG},
1839 {0x0004, SIERRA_PSC_LN_A4_PREG},
1840 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1841 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1842 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1843 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1844 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1845 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1846 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1847 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1848 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1849 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1850 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1851 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1852 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1853 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1854 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1855 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1856 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1857 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1858 {0x0041, SIERRA_DEQ_GLUT0},
1859 {0x0082, SIERRA_DEQ_GLUT1},
1860 {0x00C3, SIERRA_DEQ_GLUT2},
1861 {0x0145, SIERRA_DEQ_GLUT3},
1862 {0x0186, SIERRA_DEQ_GLUT4},
1863 {0x09E7, SIERRA_DEQ_ALUT0},
1864 {0x09A6, SIERRA_DEQ_ALUT1},
1865 {0x0965, SIERRA_DEQ_ALUT2},
1866 {0x08E3, SIERRA_DEQ_ALUT3},
1867 {0x00FA, SIERRA_DEQ_DFETAP0},
1868 {0x00FA, SIERRA_DEQ_DFETAP1},
1869 {0x00FA, SIERRA_DEQ_DFETAP2},
1870 {0x00FA, SIERRA_DEQ_DFETAP3},
1871 {0x00FA, SIERRA_DEQ_DFETAP4},
1872 {0x000F, SIERRA_DEQ_PRECUR_PREG},
1873 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1874 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1875 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1876 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1877 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1878 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1879 {0x002B, SIERRA_CPI_TRIM_PREG},
1880 {0x0003, SIERRA_EPI_CTRL_PREG},
1881 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1882 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1883 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1884 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
1903 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1904 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1905 {0x0004, SIERRA_PSC_LN_A3_PREG},
1906 {0x0004, SIERRA_PSC_LN_A4_PREG},
1907 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1908 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1909 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1910 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1911 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1912 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1913 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1914 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1915 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1916 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1917 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1918 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1919 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1920 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1921 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1922 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1923 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1924 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1925 {0x0041, SIERRA_DEQ_GLUT0},
1926 {0x0082, SIERRA_DEQ_GLUT1},
1927 {0x00C3, SIERRA_DEQ_GLUT2},
1928 {0x0145, SIERRA_DEQ_GLUT3},
1929 {0x0186, SIERRA_DEQ_GLUT4},
1930 {0x09E7, SIERRA_DEQ_ALUT0},
1931 {0x09A6, SIERRA_DEQ_ALUT1},
1932 {0x0965, SIERRA_DEQ_ALUT2},
1933 {0x08E3, SIERRA_DEQ_ALUT3},
1934 {0x00FA, SIERRA_DEQ_DFETAP0},
1935 {0x00FA, SIERRA_DEQ_DFETAP1},
1936 {0x00FA, SIERRA_DEQ_DFETAP2},
1937 {0x00FA, SIERRA_DEQ_DFETAP3},
1938 {0x00FA, SIERRA_DEQ_DFETAP4},
1939 {0x000F, SIERRA_DEQ_PRECUR_PREG},
1940 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
1941 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
1942 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1943 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
1944 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
1945 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
1946 {0x002B, SIERRA_CPI_TRIM_PREG},
1947 {0x0003, SIERRA_EPI_CTRL_PREG},
1948 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
1949 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
1950 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1951 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
1952 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
1962 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
1963 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
1964 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
1965 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
1966 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
1974 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
1975 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1976 {0x0004, SIERRA_PSC_LN_A3_PREG},
1977 {0x0004, SIERRA_PSC_LN_A4_PREG},
1978 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
1979 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
1980 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
1981 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
1982 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
1983 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
1984 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1985 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1986 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
1987 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
1988 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1989 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1990 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1991 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1992 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
1993 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1994 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
1995 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
1996 {0x0041, SIERRA_DEQ_GLUT0},
1997 {0x0082, SIERRA_DEQ_GLUT1},
1998 {0x00C3, SIERRA_DEQ_GLUT2},
1999 {0x0145, SIERRA_DEQ_GLUT3},
2000 {0x0186, SIERRA_DEQ_GLUT4},
2001 {0x09E7, SIERRA_DEQ_ALUT0},
2002 {0x09A6, SIERRA_DEQ_ALUT1},
2003 {0x0965, SIERRA_DEQ_ALUT2},
2004 {0x08E3, SIERRA_DEQ_ALUT3},
2005 {0x00FA, SIERRA_DEQ_DFETAP0},
2006 {0x00FA, SIERRA_DEQ_DFETAP1},
2007 {0x00FA, SIERRA_DEQ_DFETAP2},
2008 {0x00FA, SIERRA_DEQ_DFETAP3},
2009 {0x00FA, SIERRA_DEQ_DFETAP4},
2010 {0x000F, SIERRA_DEQ_PRECUR_PREG},
2011 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
2012 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2013 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2014 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2015 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2016 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2017 {0x002B, SIERRA_CPI_TRIM_PREG},
2018 {0x0003, SIERRA_EPI_CTRL_PREG},
2019 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
2020 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2021 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2022 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2041 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
2042 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2043 {0x0004, SIERRA_PSC_LN_A3_PREG},
2044 {0x0004, SIERRA_PSC_LN_A4_PREG},
2045 {0x0004, SIERRA_PSC_LN_IDLE_PREG},
2046 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
2047 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2048 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
2049 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2050 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2051 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2052 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2053 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2054 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
2055 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2056 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2057 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2058 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2059 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2060 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2061 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2062 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2063 {0x0041, SIERRA_DEQ_GLUT0},
2064 {0x0082, SIERRA_DEQ_GLUT1},
2065 {0x00C3, SIERRA_DEQ_GLUT2},
2066 {0x0145, SIERRA_DEQ_GLUT3},
2067 {0x0186, SIERRA_DEQ_GLUT4},
2068 {0x09E7, SIERRA_DEQ_ALUT0},
2069 {0x09A6, SIERRA_DEQ_ALUT1},
2070 {0x0965, SIERRA_DEQ_ALUT2},
2071 {0x08E3, SIERRA_DEQ_ALUT3},
2072 {0x00FA, SIERRA_DEQ_DFETAP0},
2073 {0x00FA, SIERRA_DEQ_DFETAP1},
2074 {0x00FA, SIERRA_DEQ_DFETAP2},
2075 {0x00FA, SIERRA_DEQ_DFETAP3},
2076 {0x00FA, SIERRA_DEQ_DFETAP4},
2077 {0x000F, SIERRA_DEQ_PRECUR_PREG},
2078 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
2079 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2080 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2081 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2082 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2083 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2084 {0x002B, SIERRA_CPI_TRIM_PREG},
2085 {0x0003, SIERRA_EPI_CTRL_PREG},
2086 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
2087 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2088 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2089 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},
2090 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG}
2100 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2101 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2102 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
2103 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
2108 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
2109 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2110 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
2111 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2112 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2113 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2114 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2115 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2116 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2117 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
2118 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2119 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2120 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2121 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2122 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2123 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2124 {0x0041, SIERRA_DEQ_GLUT0},
2125 {0x0082, SIERRA_DEQ_GLUT1},
2126 {0x00C3, SIERRA_DEQ_GLUT2},
2127 {0x0145, SIERRA_DEQ_GLUT3},
2128 {0x0186, SIERRA_DEQ_GLUT4},
2129 {0x09E7, SIERRA_DEQ_ALUT0},
2130 {0x09A6, SIERRA_DEQ_ALUT1},
2131 {0x0965, SIERRA_DEQ_ALUT2},
2132 {0x08E3, SIERRA_DEQ_ALUT3},
2133 {0x00FA, SIERRA_DEQ_DFETAP0},
2134 {0x00FA, SIERRA_DEQ_DFETAP1},
2135 {0x00FA, SIERRA_DEQ_DFETAP2},
2136 {0x00FA, SIERRA_DEQ_DFETAP3},
2137 {0x00FA, SIERRA_DEQ_DFETAP4},
2138 {0x000F, SIERRA_DEQ_PRECUR_PREG},
2139 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
2140 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2141 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2142 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2143 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2144 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2145 {0x002B, SIERRA_CPI_TRIM_PREG},
2146 {0x0003, SIERRA_EPI_CTRL_PREG},
2147 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
2148 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2149 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2150 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2165 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
2166 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2167 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2168 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
2169 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2170 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
2171 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
2172 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
2173 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
2174 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
2175 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
2180 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
2181 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2182 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
2183 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2184 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
2185 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2186 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2187 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2188 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2189 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2190 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
2191 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2192 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2193 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2194 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2195 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2196 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2197 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2198 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2199 {0x0041, SIERRA_DEQ_GLUT0},
2200 {0x0082, SIERRA_DEQ_GLUT1},
2201 {0x00C3, SIERRA_DEQ_GLUT2},
2202 {0x0145, SIERRA_DEQ_GLUT3},
2203 {0x0186, SIERRA_DEQ_GLUT4},
2204 {0x09E7, SIERRA_DEQ_ALUT0},
2205 {0x09A6, SIERRA_DEQ_ALUT1},
2206 {0x0965, SIERRA_DEQ_ALUT2},
2207 {0x08E3, SIERRA_DEQ_ALUT3},
2208 {0x00FA, SIERRA_DEQ_DFETAP0},
2209 {0x00FA, SIERRA_DEQ_DFETAP1},
2210 {0x00FA, SIERRA_DEQ_DFETAP2},
2211 {0x00FA, SIERRA_DEQ_DFETAP3},
2212 {0x00FA, SIERRA_DEQ_DFETAP4},
2213 {0x000F, SIERRA_DEQ_PRECUR_PREG},
2214 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
2215 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2216 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2217 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2218 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2219 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2220 {0x002B, SIERRA_CPI_TRIM_PREG},
2221 {0x0003, SIERRA_EPI_CTRL_PREG},
2222 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
2223 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2224 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2225 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2240 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2241 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2242 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
2243 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2244 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
2249 {0xFC08, SIERRA_DET_STANDEC_A_PREG},
2250 {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
2251 {0x1555, SIERRA_DFE_BIASTRIM_PREG},
2252 {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
2253 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
2254 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
2255 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
2256 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2257 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2258 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
2259 {0x9800, SIERRA_RX_CTLE_CAL_PREG},
2260 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2261 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2262 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2263 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2264 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2265 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2266 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
2267 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
2268 {0x0041, SIERRA_DEQ_GLUT0},
2269 {0x0082, SIERRA_DEQ_GLUT1},
2270 {0x00C3, SIERRA_DEQ_GLUT2},
2271 {0x0145, SIERRA_DEQ_GLUT3},
2272 {0x0186, SIERRA_DEQ_GLUT4},
2273 {0x09E7, SIERRA_DEQ_ALUT0},
2274 {0x09A6, SIERRA_DEQ_ALUT1},
2275 {0x0965, SIERRA_DEQ_ALUT2},
2276 {0x08E3, SIERRA_DEQ_ALUT3},
2277 {0x00FA, SIERRA_DEQ_DFETAP0},
2278 {0x00FA, SIERRA_DEQ_DFETAP1},
2279 {0x00FA, SIERRA_DEQ_DFETAP2},
2280 {0x00FA, SIERRA_DEQ_DFETAP3},
2281 {0x00FA, SIERRA_DEQ_DFETAP4},
2282 {0x000F, SIERRA_DEQ_PRECUR_PREG},
2283 {0x0280, SIERRA_DEQ_POSTCUR_PREG},
2284 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
2285 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2286 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
2287 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
2288 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},
2289 {0x002B, SIERRA_CPI_TRIM_PREG},
2290 {0x0003, SIERRA_EPI_CTRL_PREG},
2291 {0x803F, SIERRA_SDFILT_H2L_A_PREG},
2292 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
2293 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2294 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
2309 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
2310 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2311 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2312 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
2317 {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
2318 {0x000F, SIERRA_DET_STANDEC_B_PREG},
2319 {0x55A5, SIERRA_DET_STANDEC_C_PREG},
2320 {0x69ad, SIERRA_DET_STANDEC_D_PREG},
2321 {0x0241, SIERRA_DET_STANDEC_E_PREG},
2322 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
2323 {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
2324 {0xCF00, SIERRA_PSM_DIAG_PREG},
2325 {0x001F, SIERRA_PSC_TX_A0_PREG},
2326 {0x0007, SIERRA_PSC_TX_A1_PREG},
2327 {0x0003, SIERRA_PSC_TX_A2_PREG},
2328 {0x0003, SIERRA_PSC_TX_A3_PREG},
2329 {0x0FFF, SIERRA_PSC_RX_A0_PREG},
2330 {0x0003, SIERRA_PSC_RX_A1_PREG},
2331 {0x0003, SIERRA_PSC_RX_A2_PREG},
2332 {0x0001, SIERRA_PSC_RX_A3_PREG},
2333 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
2334 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
2335 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
2336 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
2337 {0x2512, SIERRA_DFE_BIASTRIM_PREG},
2338 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
2339 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
2340 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
2341 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2342 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
2343 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
2344 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
2345 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
2346 {0x0000, SIERRA_CREQ_SPARE_PREG},
2347 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
2348 {0x8452, SIERRA_CTLELUT_CTRL_PREG},
2349 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
2350 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
2351 {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
2352 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
2353 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2354 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
2355 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
2356 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
2357 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
2358 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
2359 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
2360 {0x0014, SIERRA_DEQ_GLUT0},
2361 {0x0014, SIERRA_DEQ_GLUT1},
2362 {0x0014, SIERRA_DEQ_GLUT2},
2363 {0x0014, SIERRA_DEQ_GLUT3},
2364 {0x0014, SIERRA_DEQ_GLUT4},
2365 {0x0014, SIERRA_DEQ_GLUT5},
2366 {0x0014, SIERRA_DEQ_GLUT6},
2367 {0x0014, SIERRA_DEQ_GLUT7},
2368 {0x0014, SIERRA_DEQ_GLUT8},
2369 {0x0014, SIERRA_DEQ_GLUT9},
2370 {0x0014, SIERRA_DEQ_GLUT10},
2371 {0x0014, SIERRA_DEQ_GLUT11},
2372 {0x0014, SIERRA_DEQ_GLUT12},
2373 {0x0014, SIERRA_DEQ_GLUT13},
2374 {0x0014, SIERRA_DEQ_GLUT14},
2375 {0x0014, SIERRA_DEQ_GLUT15},
2376 {0x0014, SIERRA_DEQ_GLUT16},
2377 {0x0BAE, SIERRA_DEQ_ALUT0},
2378 {0x0AEB, SIERRA_DEQ_ALUT1},
2379 {0x0A28, SIERRA_DEQ_ALUT2},
2380 {0x0965, SIERRA_DEQ_ALUT3},
2381 {0x08A2, SIERRA_DEQ_ALUT4},
2382 {0x07DF, SIERRA_DEQ_ALUT5},
2383 {0x071C, SIERRA_DEQ_ALUT6},
2384 {0x0659, SIERRA_DEQ_ALUT7},
2385 {0x0596, SIERRA_DEQ_ALUT8},
2386 {0x0514, SIERRA_DEQ_ALUT9},
2387 {0x0492, SIERRA_DEQ_ALUT10},
2388 {0x0410, SIERRA_DEQ_ALUT11},
2389 {0x038E, SIERRA_DEQ_ALUT12},
2390 {0x030C, SIERRA_DEQ_ALUT13},
2391 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
2392 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
2393 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
2394 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
2395 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
2396 {0x0033, SIERRA_DEQ_PICTRL_PREG},
2397 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
2398 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
2399 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
2400 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
2401 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
2402 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
2403 {0x000F, SIERRA_LFPSFILT_NS_PREG},
2404 {0x0009, SIERRA_LFPSFILT_RD_PREG},
2405 {0x0001, SIERRA_LFPSFILT_MP_PREG},
2406 {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
2407 {0x8013, SIERRA_SDFILT_H2L_A_PREG},
2408 {0x8009, SIERRA_SDFILT_L2H_PREG},
2409 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
2410 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
2411 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
2426 {0x0180, SIERRA_SDOSCCAL_CLK_CNT_PREG},
2427 {0x6000, SIERRA_CMN_REFRCV_PREG},
2428 {0x0031, SIERRA_CMN_RESCAL_CTRLA_PREG},
2429 {0x001C, SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG},
2430 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2431 {0x0000, SIERRA_CMN_PLLLC_LOCKSEARCH_PREG},
2432 {0x8103, SIERRA_CMN_PLLLC_CLK0_PREG},
2433 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2434 {0x0027, SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG},
2435 {0x0062, SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG},
2436 {0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
2437 {0x0000, SIERRA_CMN_PLLLC_INIT_PREG},
2438 {0x0000, SIERRA_CMN_PLLLC_ITERTMR_PREG},
2439 {0x0020, SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG},
2440 {0x0013, SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG},
2441 {0x0013, SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG},
2451 {0x691E, SIERRA_DET_STANDEC_D_PREG},
2452 {0x0FFE, SIERRA_PSC_RX_A0_PREG},
2453 {0x0104, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
2454 {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
2455 {0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
2456 {0x5234, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
2457 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
2458 {0x00AB, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2459 {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
2460 {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
2461 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
2462 {0x6320, SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG},
2463 {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
2464 {0x15A2, SIERRA_LN_SPARE_REG_PREG},
2465 {0x7900, SIERRA_DEQ_BLK_TAU_CTRL1_PREG},
2466 {0x2202, SIERRA_DEQ_BLK_TAU_CTRL4_PREG},
2467 {0x2206, SIERRA_DEQ_TAU_CTRL2_PREG},
2468 {0x0005, SIERRA_LANE_TX_RECEIVER_DETECT_PREG},
2469 {0x8001, SIERRA_CREQ_SPARE_PREG},
2470 {0x0000, SIERRA_DEQ_CONCUR_CTRL1_PREG},
2471 {0xD004, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2472 {0x0101, SIERRA_DEQ_GLUT9},
2473 {0x0101, SIERRA_DEQ_GLUT10},
2474 {0x0101, SIERRA_DEQ_GLUT11},
2475 {0x0101, SIERRA_DEQ_GLUT12},
2476 {0x0000, SIERRA_DEQ_GLUT13},
2477 {0x0000, SIERRA_DEQ_GLUT16},
2478 {0x0000, SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG},
2479 {0x0000, SIERRA_TAU_EN_CEPH2TO0_PREG},
2480 {0x0003, SIERRA_TAU_EN_CEPH5TO3_PREG},
2481 {0x0101, SIERRA_DEQ_ALUT8},
2482 {0x0101, SIERRA_DEQ_ALUT9},
2483 {0x0100, SIERRA_DEQ_ALUT10},
2484 {0x0000, SIERRA_OEPH_EN_CTRL_PREG},
2485 {0x5425, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2486 {0x7458, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
2487 {0x321F, SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG},
2497 .block_offset_shift = 0x2,
2498 .reg_offset_shift = 0x2,
2604 .block_offset_shift = 0x0,
2605 .reg_offset_shift = 0x1,