21 #define PHY_R0							0x00
22 	#define PHY_R0_PCIE_POWER_STATE				GENMASK(4, 0)
25 #define PHY_R1							0x04
26 	#define PHY_R1_PHY_TX1_TERM_OFFSET			GENMASK(4, 0)
35 #define PHY_R2							0x08
36 	#define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB			GENMASK(5, 0)
41 #define PHY_R4							0x10
42 	#define PHY_R4_PHY_CR_WRITE				BIT(0)
48 #define PHY_R5							0x14
49 	#define PHY_R5_PHY_CR_DATA_OUT				GENMASK(15, 0)
98 	return 0;  in phy_g12a_usb3_pcie_cr_bus_addr()
112 	regmap_write(priv->regmap, PHY_R4, 0);  in phy_g12a_usb3_pcie_cr_bus_read()
123 	regmap_write(priv->regmap, PHY_R4, 0);  in phy_g12a_usb3_pcie_cr_bus_read()
131 	return 0;  in phy_g12a_usb3_pcie_cr_bus_read()
161 				       (val & PHY_R5_PHY_CR_ACK) == 0,  in phy_g12a_usb3_pcie_cr_bus_write()
179 				       (val & PHY_R5_PHY_CR_ACK) == 0,  in phy_g12a_usb3_pcie_cr_bus_write()
184 	return 0;  in phy_g12a_usb3_pcie_cr_bus_write()
192 	.max_register = 0xffff,
218 	ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7));  in phy_g12a_usb3_init()
222 	ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20);  in phy_g12a_usb3_init()
228 	 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0  in phy_g12a_usb3_init()
233 	ret = regmap_read(priv->regmap_cr, 0x1006, &data);  in phy_g12a_usb3_init()
239 	data &= ~(0x7 << 8);  in phy_g12a_usb3_init()
240 	data |= (0x3 << 8);  in phy_g12a_usb3_init()
242 	ret = regmap_write(priv->regmap_cr, 0x1006, data);  in phy_g12a_usb3_init()
252 	ret = regmap_read(priv->regmap_cr, 0x1002, &data);  in phy_g12a_usb3_init()
256 	data &= ~0x3f80;  in phy_g12a_usb3_init()
257 	data |= (0x16 << 7);  in phy_g12a_usb3_init()
258 	data &= ~0x7f;  in phy_g12a_usb3_init()
259 	data |= (0x7f | BIT(14));  in phy_g12a_usb3_init()
260 	ret = regmap_write(priv->regmap_cr, 0x1002, data);  in phy_g12a_usb3_init()
265 	ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4);  in phy_g12a_usb3_init()
271 			FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));  in phy_g12a_usb3_init()
278 	return 0;  in phy_g12a_usb3_init()
286 		return 0;  in phy_g12a_usb3_pcie_power_on()
290 			   FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));  in phy_g12a_usb3_pcie_power_on()
292 	return 0;  in phy_g12a_usb3_pcie_power_on()
300 		return 0;  in phy_g12a_usb3_pcie_power_off()
304 			   FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));  in phy_g12a_usb3_pcie_power_off()
306 	return 0;  in phy_g12a_usb3_pcie_power_off()
315 		return 0;  in phy_g12a_usb3_pcie_reset()
329 	return 0;  in phy_g12a_usb3_pcie_reset()
339 	return 0;  in phy_g12a_usb3_pcie_init()
349 	return 0;  in phy_g12a_usb3_pcie_exit()
363 	mode = args->args[0];  in phy_g12a_usb3_pcie_xlate()
396 	base = devm_platform_ioremap_resource(pdev, 0);  in phy_g12a_usb3_pcie_probe()