1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * APM X-Gene SoC PMU (Performance Monitor Unit)
79 #define GET_CNTR(ev)      (ev->hw.idx)
80 #define GET_EVENTID(ev)   (ev->hw.config & 0xFFULL)
81 #define GET_AGENTID(ev)   (ev->hw.config_base & 0xFFFFFFFFUL)
82 #define GET_AGENT1ID(ev)  ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
172 	XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
173 	XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
178 	XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
179 	XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
184 	XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
185 	XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
190 	XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
215 	XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
220 	XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
225 	XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
230 	XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
235 	XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
273 	return sysfs_emit(buf, "config=0x%llx\n", pmu_attr->id);  in xgene_pmu_event_show()
280 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
281 	XGENE_PMU_EVENT_ATTR(cycle-count-div-64,		0x01),
282 	XGENE_PMU_EVENT_ATTR(read-hit,				0x02),
283 	XGENE_PMU_EVENT_ATTR(read-miss,				0x03),
284 	XGENE_PMU_EVENT_ATTR(write-need-replacement,		0x06),
285 	XGENE_PMU_EVENT_ATTR(write-not-need-replacement,	0x07),
286 	XGENE_PMU_EVENT_ATTR(tq-full,				0x08),
287 	XGENE_PMU_EVENT_ATTR(ackq-full,				0x09),
288 	XGENE_PMU_EVENT_ATTR(wdb-full,				0x0a),
289 	XGENE_PMU_EVENT_ATTR(bank-fifo-full,			0x0b),
290 	XGENE_PMU_EVENT_ATTR(odb-full,				0x0c),
291 	XGENE_PMU_EVENT_ATTR(wbq-full,				0x0d),
292 	XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue,		0x0e),
293 	XGENE_PMU_EVENT_ATTR(bank-fifo-issue,			0x0f),
298 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
299 	XGENE_PMU_EVENT_ATTR(cycle-count-div-64,		0x01),
300 	XGENE_PMU_EVENT_ATTR(axi0-read,				0x02),
301 	XGENE_PMU_EVENT_ATTR(axi0-read-partial,			0x03),
302 	XGENE_PMU_EVENT_ATTR(axi1-read,				0x04),
303 	XGENE_PMU_EVENT_ATTR(axi1-read-partial,			0x05),
304 	XGENE_PMU_EVENT_ATTR(csw-read-block,			0x06),
305 	XGENE_PMU_EVENT_ATTR(csw-read-partial,			0x07),
306 	XGENE_PMU_EVENT_ATTR(axi0-write,			0x10),
307 	XGENE_PMU_EVENT_ATTR(axi0-write-partial,		0x11),
308 	XGENE_PMU_EVENT_ATTR(axi1-write,			0x13),
309 	XGENE_PMU_EVENT_ATTR(axi1-write-partial,		0x14),
310 	XGENE_PMU_EVENT_ATTR(csw-inbound-dirty,			0x16),
315 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
316 	XGENE_PMU_EVENT_ATTR(cycle-count-div-64,		0x01),
317 	XGENE_PMU_EVENT_ATTR(csw-read,				0x02),
318 	XGENE_PMU_EVENT_ATTR(csw-write-request,			0x03),
319 	XGENE_PMU_EVENT_ATTR(mcb-csw-stall,			0x04),
320 	XGENE_PMU_EVENT_ATTR(cancel-read-gack,			0x05),
325 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
326 	XGENE_PMU_EVENT_ATTR(cycle-count-div-64,		0x01),
327 	XGENE_PMU_EVENT_ATTR(act-cmd-sent,			0x02),
328 	XGENE_PMU_EVENT_ATTR(pre-cmd-sent,			0x03),
329 	XGENE_PMU_EVENT_ATTR(rd-cmd-sent,			0x04),
330 	XGENE_PMU_EVENT_ATTR(rda-cmd-sent,			0x05),
331 	XGENE_PMU_EVENT_ATTR(wr-cmd-sent,			0x06),
332 	XGENE_PMU_EVENT_ATTR(wra-cmd-sent,			0x07),
333 	XGENE_PMU_EVENT_ATTR(pde-cmd-sent,			0x08),
334 	XGENE_PMU_EVENT_ATTR(sre-cmd-sent,			0x09),
335 	XGENE_PMU_EVENT_ATTR(prea-cmd-sent,			0x0a),
336 	XGENE_PMU_EVENT_ATTR(ref-cmd-sent,			0x0b),
337 	XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent,			0x0c),
338 	XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent,			0x0d),
339 	XGENE_PMU_EVENT_ATTR(in-rd-collision,			0x0e),
340 	XGENE_PMU_EVENT_ATTR(in-wr-collision,			0x0f),
341 	XGENE_PMU_EVENT_ATTR(collision-queue-not-empty,		0x10),
342 	XGENE_PMU_EVENT_ATTR(collision-queue-full,		0x11),
343 	XGENE_PMU_EVENT_ATTR(mcu-request,			0x12),
344 	XGENE_PMU_EVENT_ATTR(mcu-rd-request,			0x13),
345 	XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request,			0x14),
346 	XGENE_PMU_EVENT_ATTR(mcu-wr-request,			0x15),
347 	XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all,		0x16),
348 	XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel,		0x17),
349 	XGENE_PMU_EVENT_ATTR(mcu-rd-response,			0x18),
350 	XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all,	0x19),
351 	XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel,	0x1a),
352 	XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all,		0x1b),
353 	XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel,		0x1c),
378 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
379 	XGENE_PMU_EVENT_ATTR(read-hit,				0x01),
380 	XGENE_PMU_EVENT_ATTR(read-miss,				0x02),
381 	XGENE_PMU_EVENT_ATTR(index-flush-eviction,		0x03),
382 	XGENE_PMU_EVENT_ATTR(write-caused-replacement,		0x04),
383 	XGENE_PMU_EVENT_ATTR(write-not-caused-replacement,	0x05),
384 	XGENE_PMU_EVENT_ATTR(clean-eviction,			0x06),
385 	XGENE_PMU_EVENT_ATTR(dirty-eviction,			0x07),
389 	XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall,	0x0b),
390 	XGENE_PMU_EVENT_ATTR(tq-full,				0x0c),
391 	XGENE_PMU_EVENT_ATTR(ackq-full,				0x0d),
392 	XGENE_PMU_EVENT_ATTR(wdb-full,				0x0e),
393 	XGENE_PMU_EVENT_ATTR(odb-full,				0x10),
394 	XGENE_PMU_EVENT_ATTR(wbq-full,				0x11),
395 	XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall,	0x12),
396 	XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall,	0x13),
397 	XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall,	0x14),
398 	XGENE_PMU_EVENT_ATTR(total-insertion,			0x15),
399 	XGENE_PMU_EVENT_ATTR(sip-insertions-r-set,		0x16),
400 	XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear,		0x17),
401 	XGENE_PMU_EVENT_ATTR(dip-insertions-r-set,		0x18),
402 	XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear,		0x19),
403 	XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set,	0x1a),
406 	XGENE_PMU_EVENT_ATTR(old-replacement,			0x1d),
407 	XGENE_PMU_EVENT_ATTR(young-replacement,			0x1e),
408 	XGENE_PMU_EVENT_ATTR(r-set-replacement,			0x1f),
409 	XGENE_PMU_EVENT_ATTR(r-clear-replacement,		0x20),
410 	XGENE_PMU_EVENT_ATTR(old-r-replacement,			0x21),
411 	XGENE_PMU_EVENT_ATTR(old-nr-replacement,		0x22),
412 	XGENE_PMU_EVENT_ATTR(young-r-replacement,		0x23),
413 	XGENE_PMU_EVENT_ATTR(young-nr-replacement,		0x24),
414 	XGENE_PMU_EVENT_ATTR(bloomfilter-clearing,		0x25),
415 	XGENE_PMU_EVENT_ATTR(generation-flip,			0x26),
416 	XGENE_PMU_EVENT_ATTR(vcc-droop-detected,		0x27),
421 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
422 	XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all,		0x01),
423 	XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd,		0x02),
424 	XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr,		0x03),
425 	XGENE_PMU_EVENT_ATTR(pa-all-cp-req,			0x04),
426 	XGENE_PMU_EVENT_ATTR(pa-cp-blk-req,			0x05),
427 	XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req,			0x06),
428 	XGENE_PMU_EVENT_ATTR(pa-cp-rd-req,			0x07),
429 	XGENE_PMU_EVENT_ATTR(pa-cp-wr-req,			0x08),
430 	XGENE_PMU_EVENT_ATTR(ba-all-req,			0x09),
431 	XGENE_PMU_EVENT_ATTR(ba-rd-req,				0x0a),
432 	XGENE_PMU_EVENT_ATTR(ba-wr-req,				0x0b),
433 	XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued,		0x10),
434 	XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued,	0x11),
435 	XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
436 	XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
437 	XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable,	0x14),
438 	XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
439 	XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req,			0x16),
440 	XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req,			0x17),
441 	XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data,		0x18),
442 	XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS,	0x1b),
443 	XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence,		0x1c),
444 	XGENE_PMU_EVENT_ATTR(pa-barrier-cycles,			0x1d),
445 	XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops,		0x20),
446 	XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop,		0x21),
447 	XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit,		0x22),
448 	XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop,		0x23),
449 	XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit,		0x24),
450 	XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop,		0x25),
451 	XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit,	0x26),
452 	XGENE_PMU_EVENT_ATTR(pa-req-buffer-full,		0x28),
453 	XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full,	0x29),
454 	XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
455 	XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full,	0x2b),
456 	XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
457 	XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full,	0x2d),
458 	XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
459 	XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure,	0x2f),
464 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
465 	XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req,			0x01),
466 	XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req,			0x02),
467 	XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req,			0x03),
468 	XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req,			0x04),
469 	XGENE_PMU_EVENT_ATTR(ba-all-axi-req,			0x07),
470 	XGENE_PMU_EVENT_ATTR(ba-axi-rd-req,			0x08),
471 	XGENE_PMU_EVENT_ATTR(ba-axi-wr-req,			0x09),
472 	XGENE_PMU_EVENT_ATTR(ba-free-list-empty,		0x10),
477 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
478 	XGENE_PMU_EVENT_ATTR(req-receive,			0x01),
479 	XGENE_PMU_EVENT_ATTR(rd-req-recv,			0x02),
480 	XGENE_PMU_EVENT_ATTR(rd-req-recv-2,			0x03),
481 	XGENE_PMU_EVENT_ATTR(wr-req-recv,			0x04),
482 	XGENE_PMU_EVENT_ATTR(wr-req-recv-2,			0x05),
483 	XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu,		0x06),
484 	XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2,		0x07),
485 	XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu,		0x08),
486 	XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2,		0x09),
487 	XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
488 	XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
489 	XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
490 	XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req,	0x0d),
491 	XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2,	0x0e),
492 	XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu,		0x0f),
493 	XGENE_PMU_EVENT_ATTR(gack-recv,				0x10),
494 	XGENE_PMU_EVENT_ATTR(rd-gack-recv,			0x11),
495 	XGENE_PMU_EVENT_ATTR(wr-gack-recv,			0x12),
496 	XGENE_PMU_EVENT_ATTR(cancel-rd-gack,			0x13),
497 	XGENE_PMU_EVENT_ATTR(cancel-wr-gack,			0x14),
498 	XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall,			0x15),
499 	XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked,		0x16),
500 	XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall,		0x17),
501 	XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked,		0x18),
502 	XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked,	0x19),
503 	XGENE_PMU_EVENT_ATTR(mcu-req-table-full,		0x1a),
504 	XGENE_PMU_EVENT_ATTR(mcu-stat-table-full,		0x1b),
505 	XGENE_PMU_EVENT_ATTR(mcu-wr-table-full,			0x1c),
506 	XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp,		0x1d),
507 	XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp,		0x1e),
508 	XGENE_PMU_EVENT_ATTR(mcu-retryack-resp,			0x1f),
509 	XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp,		0x20),
510 	XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload,		0x21),
511 	XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass,		0x22),
512 	XGENE_PMU_EVENT_ATTR(volt-droop-detect,			0x23),
517 	XGENE_PMU_EVENT_ATTR(cycle-count,			0x00),
518 	XGENE_PMU_EVENT_ATTR(act-sent,				0x01),
519 	XGENE_PMU_EVENT_ATTR(pre-sent,				0x02),
520 	XGENE_PMU_EVENT_ATTR(rd-sent,				0x03),
521 	XGENE_PMU_EVENT_ATTR(rda-sent,				0x04),
522 	XGENE_PMU_EVENT_ATTR(wr-sent,				0x05),
523 	XGENE_PMU_EVENT_ATTR(wra-sent,				0x06),
524 	XGENE_PMU_EVENT_ATTR(pd-entry-vld,			0x07),
525 	XGENE_PMU_EVENT_ATTR(sref-entry-vld,			0x08),
526 	XGENE_PMU_EVENT_ATTR(prea-sent,				0x09),
527 	XGENE_PMU_EVENT_ATTR(ref-sent,				0x0a),
528 	XGENE_PMU_EVENT_ATTR(rd-rda-sent,			0x0b),
529 	XGENE_PMU_EVENT_ATTR(wr-wra-sent,			0x0c),
530 	XGENE_PMU_EVENT_ATTR(raw-hazard,			0x0d),
531 	XGENE_PMU_EVENT_ATTR(war-hazard,			0x0e),
532 	XGENE_PMU_EVENT_ATTR(waw-hazard,			0x0f),
533 	XGENE_PMU_EVENT_ATTR(rar-hazard,			0x10),
534 	XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard,		0x11),
535 	XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld,		0x12),
536 	XGENE_PMU_EVENT_ATTR(lprd-req-vld,			0x13),
537 	XGENE_PMU_EVENT_ATTR(hprd-req-vld,			0x14),
538 	XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld,			0x15),
539 	XGENE_PMU_EVENT_ATTR(wr-req-vld,			0x16),
540 	XGENE_PMU_EVENT_ATTR(partial-wr-req-vld,		0x17),
541 	XGENE_PMU_EVENT_ATTR(rd-retry,				0x18),
542 	XGENE_PMU_EVENT_ATTR(wr-retry,				0x19),
543 	XGENE_PMU_EVENT_ATTR(retry-gnt,				0x1a),
544 	XGENE_PMU_EVENT_ATTR(rank-change,			0x1b),
545 	XGENE_PMU_EVENT_ATTR(dir-change,			0x1c),
546 	XGENE_PMU_EVENT_ATTR(rank-dir-change,			0x1d),
547 	XGENE_PMU_EVENT_ATTR(rank-active,			0x1e),
548 	XGENE_PMU_EVENT_ATTR(rank-idle,				0x1f),
549 	XGENE_PMU_EVENT_ATTR(rank-pd,				0x20),
550 	XGENE_PMU_EVENT_ATTR(rank-sref,				0x21),
551 	XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh,		0x22),
552 	XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh,		0x23),
553 	XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh,		0x24),
554 	XGENE_PMU_EVENT_ATTR(phy-updt-complt,			0x25),
555 	XGENE_PMU_EVENT_ATTR(tz-fail,				0x26),
556 	XGENE_PMU_EVENT_ATTR(dram-errc,				0x27),
557 	XGENE_PMU_EVENT_ATTR(dram-errd,				0x28),
558 	XGENE_PMU_EVENT_ATTR(rd-enq,				0x29),
559 	XGENE_PMU_EVENT_ATTR(wr-enq,				0x2a),
560 	XGENE_PMU_EVENT_ATTR(tmac-limit-reached,		0x2b),
561 	XGENE_PMU_EVENT_ATTR(tmaw-tracker-full,			0x2c),
598 	return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);  in cpumask_show()
685 	cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,  in get_next_avail_cntr()
686 				pmu_dev->max_counters);  in get_next_avail_cntr()
687 	if (cntr == pmu_dev->max_counters)  in get_next_avail_cntr()
688 		return -ENOSPC;  in get_next_avail_cntr()
689 	set_bit(cntr, pmu_dev->cntr_assign_mask);  in get_next_avail_cntr()
696 	clear_bit(cntr, pmu_dev->cntr_assign_mask);  in clear_avail_cntr()
701 	writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);  in xgene_pmu_mask_int()
706 	writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);  in xgene_pmu_v3_mask_int()
711 	writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);  in xgene_pmu_unmask_int()
717 	       xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);  in xgene_pmu_v3_unmask_int()
723 	return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_read_counter32()
732 	 * v3 has 64-bit counter registers composed by 2 32-bit registers  in xgene_pmu_read_counter64()
748 	writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_write_counter32()
759 	/* v3 has 64-bit counter registers composed by 2 32-bit registers */  in xgene_pmu_write_counter64()
767 	writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));  in xgene_pmu_write_evttype()
773 	writel(val, pmu_dev->inf->csr + PMU_PMAMR0);  in xgene_pmu_write_agentmsk()
782 	writel(val, pmu_dev->inf->csr + PMU_PMAMR1);  in xgene_pmu_write_agent1msk()
793 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
795 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
803 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
805 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
813 	val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
815 	writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
823 	val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
825 	writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
832 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
834 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
841 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
843 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
850 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
852 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
858 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_pmu_enable()
859 	bool enabled = !bitmap_empty(pmu_dev->cntr_assign_mask,  in xgene_perf_pmu_enable()
860 			pmu_dev->max_counters);  in xgene_perf_pmu_enable()
865 	xgene_pmu->ops->start_counters(pmu_dev);  in xgene_perf_pmu_enable()
871 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_pmu_disable()
873 	xgene_pmu->ops->stop_counters(pmu_dev);  in xgene_perf_pmu_disable()
878 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_event_init()
879 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_event_init()
883 	if (event->attr.type != event->pmu->type)  in xgene_perf_event_init()
884 		return -ENOENT;  in xgene_perf_event_init()
888 	 * Therefore, it does not support per-process mode.  in xgene_perf_event_init()
891 	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)  in xgene_perf_event_init()
892 		return -EINVAL;  in xgene_perf_event_init()
894 	if (event->cpu < 0)  in xgene_perf_event_init()
895 		return -EINVAL;  in xgene_perf_event_init()
900 	 * but can lead to issues for off-core PMUs, where each  in xgene_perf_event_init()
905 	event->cpu = cpumask_first(&pmu_dev->parent->cpu);  in xgene_perf_event_init()
907 	hw->config = event->attr.config;  in xgene_perf_event_init()
914 	hw->config_base = event->attr.config1;  in xgene_perf_event_init()
920 	if (event->group_leader->pmu != event->pmu &&  in xgene_perf_event_init()
921 			!is_software_event(event->group_leader))  in xgene_perf_event_init()
922 		return -EINVAL;  in xgene_perf_event_init()
924 	for_each_sibling_event(sibling, event->group_leader) {  in xgene_perf_event_init()
925 		if (sibling->pmu != event->pmu &&  in xgene_perf_event_init()
927 			return -EINVAL;  in xgene_perf_event_init()
935 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_enable_event()
936 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_enable_event()
938 	xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),  in xgene_perf_enable_event()
940 	xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));  in xgene_perf_enable_event()
941 	if (pmu_dev->inf->type == PMU_TYPE_IOB)  in xgene_perf_enable_event()
942 		xgene_pmu->ops->write_agent1msk(pmu_dev,  in xgene_perf_enable_event()
945 	xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));  in xgene_perf_enable_event()
946 	xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));  in xgene_perf_enable_event()
951 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_disable_event()
952 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_disable_event()
954 	xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));  in xgene_perf_disable_event()
955 	xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));  in xgene_perf_disable_event()
960 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_event_set_period()
961 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_event_set_period()
962 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_event_set_period()
972 	local64_set(&hw->prev_count, val);  in xgene_perf_event_set_period()
973 	xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);  in xgene_perf_event_set_period()
978 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_event_update()
979 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_event_update()
980 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_event_update()
984 	prev_raw_count = local64_read(&hw->prev_count);  in xgene_perf_event_update()
985 	new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));  in xgene_perf_event_update()
987 	if (local64_cmpxchg(&hw->prev_count, prev_raw_count,  in xgene_perf_event_update()
991 	delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;  in xgene_perf_event_update()
993 	local64_add(delta, &event->count);  in xgene_perf_event_update()
1003 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_start()
1004 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in xgene_perf_start()
1005 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_start()
1007 	if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))  in xgene_perf_start()
1010 	WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));  in xgene_perf_start()
1011 	hw->state = 0;  in xgene_perf_start()
1016 		u64 prev_raw_count =  local64_read(&hw->prev_count);  in xgene_perf_start()
1018 		xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),  in xgene_perf_start()
1028 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_stop()
1030 	if (hw->state & PERF_HES_UPTODATE)  in xgene_perf_stop()
1034 	WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);  in xgene_perf_stop()
1035 	hw->state |= PERF_HES_STOPPED;  in xgene_perf_stop()
1037 	if (hw->state & PERF_HES_UPTODATE)  in xgene_perf_stop()
1041 	hw->state |= PERF_HES_UPTODATE;  in xgene_perf_stop()
1046 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_add()
1047 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_add()
1049 	hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;  in xgene_perf_add()
1052 	hw->idx = get_next_avail_cntr(pmu_dev);  in xgene_perf_add()
1053 	if (hw->idx < 0)  in xgene_perf_add()
1054 		return -EAGAIN;  in xgene_perf_add()
1057 	pmu_dev->pmu_counter_event[hw->idx] = event;  in xgene_perf_add()
1067 	struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);  in xgene_perf_del()
1068 	struct hw_perf_event *hw = &event->hw;  in xgene_perf_del()
1076 	pmu_dev->pmu_counter_event[hw->idx] = NULL;  in xgene_perf_del()
1083 	if (pmu_dev->parent->version == PCP_PMU_V3)  in xgene_init_perf()
1084 		pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;  in xgene_init_perf()
1086 		pmu_dev->max_period = PMU_CNT_MAX_PERIOD;  in xgene_init_perf()
1088 	xgene_pmu = pmu_dev->parent;  in xgene_init_perf()
1089 	if (xgene_pmu->version == PCP_PMU_V1)  in xgene_init_perf()
1090 		pmu_dev->max_counters = 1;  in xgene_init_perf()
1092 		pmu_dev->max_counters = PMU_MAX_COUNTERS;  in xgene_init_perf()
1095 	pmu_dev->pmu = (struct pmu) {  in xgene_init_perf()
1096 		.parent		= pmu_dev->parent->dev,  in xgene_init_perf()
1097 		.attr_groups	= pmu_dev->attr_groups,  in xgene_init_perf()
1111 	xgene_pmu->ops->stop_counters(pmu_dev);  in xgene_init_perf()
1112 	xgene_pmu->ops->reset_counters(pmu_dev);  in xgene_init_perf()
1114 	return perf_pmu_register(&pmu_dev->pmu, name, -1);  in xgene_init_perf()
1120 	struct device *dev = xgene_pmu->dev;  in xgene_pmu_dev_add()
1125 		return -ENOMEM;  in xgene_pmu_dev_add()
1126 	pmu->parent = xgene_pmu;  in xgene_pmu_dev_add()
1127 	pmu->inf = &ctx->inf;  in xgene_pmu_dev_add()
1128 	ctx->pmu_dev = pmu;  in xgene_pmu_dev_add()
1130 	switch (pmu->inf->type) {  in xgene_pmu_dev_add()
1132 		if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1133 			return -ENODEV;  in xgene_pmu_dev_add()
1134 		if (xgene_pmu->version == PCP_PMU_V3)  in xgene_pmu_dev_add()
1135 			pmu->attr_groups = l3c_pmu_v3_attr_groups;  in xgene_pmu_dev_add()
1137 			pmu->attr_groups = l3c_pmu_attr_groups;  in xgene_pmu_dev_add()
1140 		if (xgene_pmu->version == PCP_PMU_V3)  in xgene_pmu_dev_add()
1141 			pmu->attr_groups = iob_fast_pmu_v3_attr_groups;  in xgene_pmu_dev_add()
1143 			pmu->attr_groups = iob_pmu_attr_groups;  in xgene_pmu_dev_add()
1146 		if (xgene_pmu->version == PCP_PMU_V3)  in xgene_pmu_dev_add()
1147 			pmu->attr_groups = iob_slow_pmu_v3_attr_groups;  in xgene_pmu_dev_add()
1150 		if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1151 			return -ENODEV;  in xgene_pmu_dev_add()
1152 		if (xgene_pmu->version == PCP_PMU_V3)  in xgene_pmu_dev_add()
1153 			pmu->attr_groups = mcb_pmu_v3_attr_groups;  in xgene_pmu_dev_add()
1155 			pmu->attr_groups = mcb_pmu_attr_groups;  in xgene_pmu_dev_add()
1158 		if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1159 			return -ENODEV;  in xgene_pmu_dev_add()
1160 		if (xgene_pmu->version == PCP_PMU_V3)  in xgene_pmu_dev_add()
1161 			pmu->attr_groups = mc_pmu_v3_attr_groups;  in xgene_pmu_dev_add()
1163 			pmu->attr_groups = mc_pmu_attr_groups;  in xgene_pmu_dev_add()
1166 		return -EINVAL;  in xgene_pmu_dev_add()
1169 	if (xgene_init_perf(pmu, ctx->name)) {  in xgene_pmu_dev_add()
1170 		dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);  in xgene_pmu_dev_add()
1171 		return -ENODEV;  in xgene_pmu_dev_add()
1174 	dev_info(dev, "%s PMU registered\n", ctx->name);  in xgene_pmu_dev_add()
1181 	struct xgene_pmu *xgene_pmu = pmu_dev->parent;  in _xgene_pmu_isr()
1182 	void __iomem *csr = pmu_dev->inf->csr;  in _xgene_pmu_isr()
1186 	xgene_pmu->ops->stop_counters(pmu_dev);  in _xgene_pmu_isr()
1188 	if (xgene_pmu->version == PCP_PMU_V3)  in _xgene_pmu_isr()
1197 	if (xgene_pmu->version == PCP_PMU_V1)  in _xgene_pmu_isr()
1199 	else if (xgene_pmu->version == PCP_PMU_V2)  in _xgene_pmu_isr()
1205 		struct perf_event *event = pmu_dev->pmu_counter_event[idx];  in _xgene_pmu_isr()
1216 	xgene_pmu->ops->start_counters(pmu_dev);  in _xgene_pmu_isr()
1226 	raw_spin_lock(&xgene_pmu->lock);  in xgene_pmu_isr()
1229 	val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);  in xgene_pmu_isr()
1230 	if (xgene_pmu->version == PCP_PMU_V3) {  in xgene_pmu_isr()
1242 		list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {  in xgene_pmu_isr()
1243 			_xgene_pmu_isr(irq, ctx->pmu_dev);  in xgene_pmu_isr()
1247 		list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {  in xgene_pmu_isr()
1248 			_xgene_pmu_isr(irq, ctx->pmu_dev);  in xgene_pmu_isr()
1252 		list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {  in xgene_pmu_isr()
1253 			_xgene_pmu_isr(irq, ctx->pmu_dev);  in xgene_pmu_isr()
1257 		list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {  in xgene_pmu_isr()
1258 			_xgene_pmu_isr(irq, ctx->pmu_dev);  in xgene_pmu_isr()
1262 	raw_spin_unlock(&xgene_pmu->lock);  in xgene_pmu_isr()
1275 		dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");  in acpi_pmu_probe_active_mcb_mcu_l3c()
1281 		dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");  in acpi_pmu_probe_active_mcb_mcu_l3c()
1287 		dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");  in acpi_pmu_probe_active_mcb_mcu_l3c()
1291 	xgene_pmu->l3c_active_mask = 0x1;  in acpi_pmu_probe_active_mcb_mcu_l3c()
1296 		xgene_pmu->mcb_active_mask = 0x3;  in acpi_pmu_probe_active_mcb_mcu_l3c()
1299 		xgene_pmu->mc_active_mask =  in acpi_pmu_probe_active_mcb_mcu_l3c()
1303 		xgene_pmu->mcb_active_mask = 0x1;  in acpi_pmu_probe_active_mcb_mcu_l3c()
1306 		xgene_pmu->mc_active_mask =  in acpi_pmu_probe_active_mcb_mcu_l3c()
1323 		dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1332 		xgene_pmu->mcb_active_mask = 0x3;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1334 		xgene_pmu->l3c_active_mask = 0xFF;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1337 			xgene_pmu->mc_active_mask = 0xFF;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1339 			xgene_pmu->mc_active_mask =  0x33;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1341 			xgene_pmu->mc_active_mask =  0x11;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1344 		xgene_pmu->mcb_active_mask = 0x1;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1346 		xgene_pmu->l3c_active_mask = 0x0F;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1349 			xgene_pmu->mc_active_mask = 0x0F;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1351 			xgene_pmu->mc_active_mask =  0x03;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1353 			xgene_pmu->mc_active_mask =  0x01;  in acpi_pmu_v3_probe_active_mcb_mcu_l3c()
1363 	struct device_node *np = pdev->dev.of_node;  in fdt_pmu_probe_active_mcb_mcu_l3c()
1366 	csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");  in fdt_pmu_probe_active_mcb_mcu_l3c()
1368 		dev_err(&pdev->dev, "unable to get syscon regmap csw\n");  in fdt_pmu_probe_active_mcb_mcu_l3c()
1372 	mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");  in fdt_pmu_probe_active_mcb_mcu_l3c()
1374 		dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");  in fdt_pmu_probe_active_mcb_mcu_l3c()
1378 	mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");  in fdt_pmu_probe_active_mcb_mcu_l3c()
1380 		dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");  in fdt_pmu_probe_active_mcb_mcu_l3c()
1384 	xgene_pmu->l3c_active_mask = 0x1;  in fdt_pmu_probe_active_mcb_mcu_l3c()
1386 		return -EINVAL;  in fdt_pmu_probe_active_mcb_mcu_l3c()
1390 		xgene_pmu->mcb_active_mask = 0x3;  in fdt_pmu_probe_active_mcb_mcu_l3c()
1394 		xgene_pmu->mc_active_mask =  in fdt_pmu_probe_active_mcb_mcu_l3c()
1398 		xgene_pmu->mcb_active_mask = 0x1;  in fdt_pmu_probe_active_mcb_mcu_l3c()
1402 		xgene_pmu->mc_active_mask =  in fdt_pmu_probe_active_mcb_mcu_l3c()
1412 	if (has_acpi_companion(&pdev->dev)) {  in xgene_pmu_probe_active_mcb_mcu_l3c()
1413 		if (xgene_pmu->version == PCP_PMU_V3)  in xgene_pmu_probe_active_mcb_mcu_l3c()
1446 	struct device *dev = xgene_pmu->dev;  in acpi_get_pmu_hw_inf()
1469 		if (resource_type(rentry->res) == IORESOURCE_MEM) {  in acpi_get_pmu_hw_inf()
1470 			res = *rentry->res;  in acpi_get_pmu_hw_inf()
1488 	/* A PMU device node without enable-bit-index is always enabled */  in acpi_get_pmu_hw_inf()
1489 	rc = acpi_dev_get_property(adev, "enable-bit-index",  in acpi_get_pmu_hw_inf()
1494 		enable_bit = (int) obj->integer.value;  in acpi_get_pmu_hw_inf()
1496 	ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);  in acpi_get_pmu_hw_inf()
1497 	if (!ctx->name) {  in acpi_get_pmu_hw_inf()
1501 	inf = &ctx->inf;  in acpi_get_pmu_hw_inf()
1502 	inf->type = type;  in acpi_get_pmu_hw_inf()
1503 	inf->csr = dev_csr;  in acpi_get_pmu_hw_inf()
1504 	inf->enable_mask = 1 << enable_bit;  in acpi_get_pmu_hw_inf()
1529 	for (id = ids; id->id[0] || id->cls; id++) {  in xgene_pmu_acpi_match_type()
1547 	if (!adev || acpi_bus_get_status(adev) || !adev->status.present)  in acpi_pmu_dev_add()
1554 	ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);  in acpi_pmu_dev_add()
1560 		devm_kfree(xgene_pmu->dev, ctx);  in acpi_pmu_dev_add()
1564 	switch (ctx->inf.type) {  in acpi_pmu_dev_add()
1566 		list_add(&ctx->next, &xgene_pmu->l3cpmus);  in acpi_pmu_dev_add()
1569 		list_add(&ctx->next, &xgene_pmu->iobpmus);  in acpi_pmu_dev_add()
1572 		list_add(&ctx->next, &xgene_pmu->iobpmus);  in acpi_pmu_dev_add()
1575 		list_add(&ctx->next, &xgene_pmu->mcbpmus);  in acpi_pmu_dev_add()
1578 		list_add(&ctx->next, &xgene_pmu->mcpmus);  in acpi_pmu_dev_add()
1587 	struct device *dev = xgene_pmu->dev;  in acpi_pmu_probe_pmu_dev()
1593 		return -EINVAL;  in acpi_pmu_probe_pmu_dev()
1599 		return -ENODEV;  in acpi_pmu_probe_pmu_dev()
1616 	struct device *dev = xgene_pmu->dev;  in fdt_get_pmu_hw_inf()
1638 	/* A PMU device node without enable-bit-index is always enabled */  in fdt_get_pmu_hw_inf()
1639 	if (of_property_read_u32(np, "enable-bit-index", &enable_bit))  in fdt_get_pmu_hw_inf()
1642 	ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);  in fdt_get_pmu_hw_inf()
1643 	if (!ctx->name) {  in fdt_get_pmu_hw_inf()
1648 	inf = &ctx->inf;  in fdt_get_pmu_hw_inf()
1649 	inf->type = type;  in fdt_get_pmu_hw_inf()
1650 	inf->csr = dev_csr;  in fdt_get_pmu_hw_inf()
1651 	inf->enable_mask = 1 << enable_bit;  in fdt_get_pmu_hw_inf()
1662 	for_each_child_of_node(pdev->dev.of_node, np) {  in fdt_pmu_probe_pmu_dev()
1666 		if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))  in fdt_pmu_probe_pmu_dev()
1668 		else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))  in fdt_pmu_probe_pmu_dev()
1670 		else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))  in fdt_pmu_probe_pmu_dev()
1672 		else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))  in fdt_pmu_probe_pmu_dev()
1682 			devm_kfree(xgene_pmu->dev, ctx);  in fdt_pmu_probe_pmu_dev()
1686 		switch (ctx->inf.type) {  in fdt_pmu_probe_pmu_dev()
1688 			list_add(&ctx->next, &xgene_pmu->l3cpmus);  in fdt_pmu_probe_pmu_dev()
1691 			list_add(&ctx->next, &xgene_pmu->iobpmus);  in fdt_pmu_probe_pmu_dev()
1694 			list_add(&ctx->next, &xgene_pmu->iobpmus);  in fdt_pmu_probe_pmu_dev()
1697 			list_add(&ctx->next, &xgene_pmu->mcbpmus);  in fdt_pmu_probe_pmu_dev()
1700 			list_add(&ctx->next, &xgene_pmu->mcpmus);  in fdt_pmu_probe_pmu_dev()
1711 	if (has_acpi_companion(&pdev->dev))  in xgene_pmu_probe_pmu_dev()
1765 	{ .compatible	= "apm,xgene-pmu",	.data = &xgene_pmu_data },
1766 	{ .compatible	= "apm,xgene-pmu-v2",	.data = &xgene_pmu_v2_data },
1785 	if (cpumask_empty(&xgene_pmu->cpu))  in xgene_pmu_online_cpu()
1786 		cpumask_set_cpu(cpu, &xgene_pmu->cpu);  in xgene_pmu_online_cpu()
1789 	WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));  in xgene_pmu_online_cpu()
1801 	if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))  in xgene_pmu_offline_cpu()
1807 	list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {  in xgene_pmu_offline_cpu()
1808 		perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);  in xgene_pmu_offline_cpu()
1810 	list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {  in xgene_pmu_offline_cpu()
1811 		perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);  in xgene_pmu_offline_cpu()
1813 	list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {  in xgene_pmu_offline_cpu()
1814 		perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);  in xgene_pmu_offline_cpu()
1816 	list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {  in xgene_pmu_offline_cpu()
1817 		perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);  in xgene_pmu_offline_cpu()
1820 	cpumask_set_cpu(target, &xgene_pmu->cpu);  in xgene_pmu_offline_cpu()
1822 	WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));  in xgene_pmu_offline_cpu()
1842 	xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);  in xgene_pmu_probe()
1844 		return -ENOMEM;  in xgene_pmu_probe()
1845 	xgene_pmu->dev = &pdev->dev;  in xgene_pmu_probe()
1848 	dev_data = device_get_match_data(&pdev->dev);  in xgene_pmu_probe()
1850 		return -ENODEV;  in xgene_pmu_probe()
1851 	version = dev_data->id;  in xgene_pmu_probe()
1854 		xgene_pmu->ops = &xgene_pmu_v3_ops;  in xgene_pmu_probe()
1856 		xgene_pmu->ops = &xgene_pmu_ops;  in xgene_pmu_probe()
1858 	INIT_LIST_HEAD(&xgene_pmu->l3cpmus);  in xgene_pmu_probe()
1859 	INIT_LIST_HEAD(&xgene_pmu->iobpmus);  in xgene_pmu_probe()
1860 	INIT_LIST_HEAD(&xgene_pmu->mcbpmus);  in xgene_pmu_probe()
1861 	INIT_LIST_HEAD(&xgene_pmu->mcpmus);  in xgene_pmu_probe()
1863 	xgene_pmu->version = version;  in xgene_pmu_probe()
1864 	dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);  in xgene_pmu_probe()
1866 	xgene_pmu->pcppmu_csr = devm_platform_ioremap_resource(pdev, 0);  in xgene_pmu_probe()
1867 	if (IS_ERR(xgene_pmu->pcppmu_csr)) {  in xgene_pmu_probe()
1868 		dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");  in xgene_pmu_probe()
1869 		return PTR_ERR(xgene_pmu->pcppmu_csr);  in xgene_pmu_probe()
1874 		return -EINVAL;  in xgene_pmu_probe()
1876 	rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,  in xgene_pmu_probe()
1878 				dev_name(&pdev->dev), xgene_pmu);  in xgene_pmu_probe()
1880 		dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);  in xgene_pmu_probe()
1884 	xgene_pmu->irq = irq;  in xgene_pmu_probe()
1886 	raw_spin_lock_init(&xgene_pmu->lock);  in xgene_pmu_probe()
1891 		dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");  in xgene_pmu_probe()
1892 		xgene_pmu->mcb_active_mask = 0x1;  in xgene_pmu_probe()
1893 		xgene_pmu->mc_active_mask = 0x1;  in xgene_pmu_probe()
1898 				      &xgene_pmu->node);  in xgene_pmu_probe()
1900 		dev_err(&pdev->dev, "Error %d registering hotplug", rc);  in xgene_pmu_probe()
1907 		dev_err(&pdev->dev, "No PMU perf devices found!\n");  in xgene_pmu_probe()
1912 	xgene_pmu->ops->unmask_int(xgene_pmu);  in xgene_pmu_probe()
1918 				    &xgene_pmu->node);  in xgene_pmu_probe()
1928 		perf_pmu_unregister(&ctx->pmu_dev->pmu);  in xgene_pmu_dev_cleanup()
1934 	struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);  in xgene_pmu_remove()
1936 	xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);  in xgene_pmu_remove()
1937 	xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);  in xgene_pmu_remove()
1938 	xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);  in xgene_pmu_remove()
1939 	xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);  in xgene_pmu_remove()
1941 				    &xgene_pmu->node);  in xgene_pmu_remove()
1948 		.name		= "xgene-pmu",