Lines Matching full:pmu
52 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
66 const char *identifier; /* system PMU identifier for userspace */
101 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
102 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
103 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
104 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
105 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
106 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
107 { .compatible = "fsl,imx8dxl-ddr-pmu", .data = &imx8dxl_devtype_data},
113 struct pmu pmu; member
130 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
132 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
140 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_attr_visible() local
142 if (!pmu->devtype_data->identifier) in ddr_perf_identifier_attr_visible()
167 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) in ddr_perf_filter_cap_get() argument
169 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
190 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_filter_cap_show() local
195 return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap)); in ddr_perf_filter_cap_show()
221 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
223 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
344 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_is_enhanced_filtered() local
346 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED; in ddr_perf_is_enhanced_filtered()
351 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) in ddr_perf_alloc_counter() argument
361 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL) in ddr_perf_alloc_counter()
368 if (pmu->events[i] == NULL) in ddr_perf_alloc_counter()
375 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_free_counter() argument
377 pmu->events[counter] = NULL; in ddr_perf_free_counter()
380 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_read_counter() argument
382 struct perf_event *event = pmu->events[counter]; in ddr_perf_read_counter()
383 void __iomem *base = pmu->base; in ddr_perf_read_counter()
387 * axid-read and axid-write event if PMU core supports enhanced in ddr_perf_read_counter()
397 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_init() local
401 if (event->attr.type != event->pmu->type) in ddr_perf_event_init()
408 dev_warn(pmu->dev, "Can't provide per-task data!\n"); in ddr_perf_event_init()
417 if (event->group_leader->pmu != event->pmu && in ddr_perf_event_init()
421 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { in ddr_perf_event_init()
431 if (sibling->pmu != event->pmu && in ddr_perf_event_init()
436 event->cpu = pmu->cpu; in ddr_perf_event_init()
442 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, in ddr_perf_counter_enable() argument
455 writel(0, pmu->base + reg); in ddr_perf_counter_enable()
464 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { in ddr_perf_counter_enable()
469 writel(val, pmu->base + reg); in ddr_perf_counter_enable()
472 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; in ddr_perf_counter_enable()
473 writel(val, pmu->base + reg); in ddr_perf_counter_enable()
477 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) in ddr_perf_counter_overflow() argument
481 val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); in ddr_perf_counter_overflow()
486 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter) in ddr_perf_counter_clear() argument
491 val = readl_relaxed(pmu->base + reg); in ddr_perf_counter_clear()
493 writel(val, pmu->base + reg); in ddr_perf_counter_clear()
496 writel(val, pmu->base + reg); in ddr_perf_counter_clear()
501 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_update() local
507 new_raw_count = ddr_perf_read_counter(pmu, counter); in ddr_perf_event_update()
509 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { in ddr_perf_event_update()
523 ret = ddr_perf_counter_overflow(pmu, counter); in ddr_perf_event_update()
525 dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n", in ddr_perf_event_update()
530 ddr_perf_counter_clear(pmu, counter); in ddr_perf_event_update()
535 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_start() local
541 ddr_perf_counter_enable(pmu, event->attr.config, counter, true); in ddr_perf_event_start()
543 if (!pmu->active_counter++) in ddr_perf_event_start()
544 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, in ddr_perf_event_start()
552 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_add() local
559 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { in ddr_perf_event_add()
563 if (pmu->events[i] && in ddr_perf_event_add()
564 !ddr_perf_filters_compatible(event, pmu->events[i])) in ddr_perf_event_add()
571 writel(cfg1, pmu->base + COUNTER_DPCR1); in ddr_perf_event_add()
575 counter = ddr_perf_alloc_counter(pmu, cfg); in ddr_perf_event_add()
577 dev_dbg(pmu->dev, "There are not enough counters\n"); in ddr_perf_event_add()
581 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER) { in ddr_perf_event_add()
585 writel(cfg1, pmu->base + COUNTER_MASK_COMP + ((counter - 1) << 4)); in ddr_perf_event_add()
597 writel(cfg2, pmu->base + COUNTER_MUX_CNTL + ((counter - 1) << 4)); in ddr_perf_event_add()
601 pmu->events[counter] = event; in ddr_perf_event_add()
614 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_stop() local
618 ddr_perf_counter_enable(pmu, event->attr.config, counter, false); in ddr_perf_event_stop()
621 if (!--pmu->active_counter) in ddr_perf_event_stop()
622 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, in ddr_perf_event_stop()
630 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_del() local
636 ddr_perf_free_counter(pmu, counter); in ddr_perf_event_del()
640 static void ddr_perf_pmu_enable(struct pmu *pmu) in ddr_perf_pmu_enable() argument
644 static void ddr_perf_pmu_disable(struct pmu *pmu) in ddr_perf_pmu_disable() argument
648 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, in ddr_perf_init() argument
651 *pmu = (struct ddr_pmu) { in ddr_perf_init()
652 .pmu = (struct pmu) { in ddr_perf_init()
671 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL); in ddr_perf_init()
672 return pmu->id; in ddr_perf_init()
678 struct ddr_pmu *pmu = (struct ddr_pmu *) p; in ddr_perf_irq_handler() local
682 ddr_perf_counter_enable(pmu, in ddr_perf_irq_handler()
700 if (!pmu->events[i]) in ddr_perf_irq_handler()
703 event = pmu->events[i]; in ddr_perf_irq_handler()
708 ddr_perf_counter_enable(pmu, in ddr_perf_irq_handler()
718 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); in ddr_perf_offline_cpu() local
721 if (cpu != pmu->cpu) in ddr_perf_offline_cpu()
728 perf_pmu_migrate_context(&pmu->pmu, cpu, target); in ddr_perf_offline_cpu()
729 pmu->cpu = target; in ddr_perf_offline_cpu()
731 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); in ddr_perf_offline_cpu()
738 struct ddr_pmu *pmu; in ddr_perf_probe() local
752 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); in ddr_perf_probe()
753 if (!pmu) in ddr_perf_probe()
756 num = ddr_perf_init(pmu, base, &pdev->dev); in ddr_perf_probe()
758 platform_set_drvdata(pdev, pmu); in ddr_perf_probe()
767 pmu->devtype_data = of_device_get_match_data(&pdev->dev); in ddr_perf_probe()
769 pmu->cpu = raw_smp_processor_id(); in ddr_perf_probe()
780 pmu->cpuhp_state = ret; in ddr_perf_probe()
782 /* Register the pmu instance for cpu hotplug */ in ddr_perf_probe()
783 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
801 pmu); in ddr_perf_probe()
807 pmu->irq = irq; in ddr_perf_probe()
808 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); in ddr_perf_probe()
810 dev_err(pmu->dev, "Failed to set interrupt affinity!\n"); in ddr_perf_probe()
814 ret = perf_pmu_register(&pmu->pmu, name, -1); in ddr_perf_probe()
821 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
823 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_probe()
825 ida_free(&ddr_ida, pmu->id); in ddr_perf_probe()
826 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret); in ddr_perf_probe()
832 struct ddr_pmu *pmu = platform_get_drvdata(pdev); in ddr_perf_remove() local
834 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_remove()
835 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_remove()
837 perf_pmu_unregister(&pmu->pmu); in ddr_perf_remove()
839 ida_free(&ddr_ida, pmu->id); in ddr_perf_remove()
844 .name = "imx-ddr-pmu",