Lines Matching +full:1 +full:c12
661 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
662 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
663 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
664 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
665 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
666 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
693 #define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */
698 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); in armv7_pmnc_read()
706 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); in armv7_pmnc_write()
726 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx)); in armv7_pmnc_select_counter()
771 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); in armv7_pmnc_write_evtsel()
776 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(idx))); in armv7_pmnc_enable_counter()
781 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(idx))); in armv7_pmnc_disable_counter()
786 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(idx))); in armv7_pmnc_enable_intens()
794 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(idx))); in armv7_pmnc_disable_intens()
803 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); in armv7_pmnc_getreset_flags()
807 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); in armv7_pmnc_getreset_flags()
820 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); in armv7_pmnc_dump_regs()
823 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
826 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
829 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); in armv7_pmnc_dump_regs()
832 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); in armv7_pmnc_dump_regs()
842 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
1058 asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); in armv7pmu_reset()
1060 asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); in armv7pmu_reset()
1158 arm_pmu, 1); in armv7_probe_num_events()
1252 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0
1254 * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1
1256 * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2
1260 * EN | G=3 | G=2 | G=1 | G=0
1266 * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR)
1271 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
1280 #define KRAIT_EVENT (1 << 16)
1289 #define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */
1297 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); in krait_read_pmresrn()
1299 case 1: in krait_read_pmresrn()
1300 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); in krait_read_pmresrn()
1303 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); in krait_read_pmresrn()
1316 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); in krait_write_pmresrn()
1318 case 1: in krait_write_pmresrn()
1319 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); in krait_write_pmresrn()
1322 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); in krait_write_pmresrn()
1514 krait_write_pmresrn(1, 0); in krait_pmu_reset()
1559 int bit = -1; in krait_pmu_get_event_idx()
1627 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0
1629 * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1
1631 * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2
1633 * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3
1637 * EN | G=3 | G=2 | G=1 | G=0
1644 * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM)
1649 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
1666 case 1: in scorpion_read_pmresrn()
1667 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1688 case 1: in scorpion_write_pmresrn()
1689 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1835 scorpion_write_pmresrn(1, 0); in scorpion_pmu_reset()
1880 int bit = -1; in scorpion_pmu_get_event_idx()