Lines Matching +full:0 +full:x1801
37 #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
38 #define TI113X_SCR_SMIROUTE 0x04000000
39 #define TI113X_SCR_SMISTATUS 0x02000000
40 #define TI113X_SCR_SMIENB 0x01000000
41 #define TI113X_SCR_VCCPROT 0x00200000
42 #define TI113X_SCR_REDUCEZV 0x00100000
43 #define TI113X_SCR_CDREQEN 0x00080000
44 #define TI113X_SCR_CDMACHAN 0x00070000
45 #define TI113X_SCR_SOCACTIVE 0x00002000
46 #define TI113X_SCR_PWRSTREAM 0x00000800
47 #define TI113X_SCR_DELAYUP 0x00000400
48 #define TI113X_SCR_DELAYDOWN 0x00000200
49 #define TI113X_SCR_INTERROGATE 0x00000100
50 #define TI113X_SCR_CLKRUN_SEL 0x00000080
51 #define TI113X_SCR_PWRSAVINGS 0x00000040
52 #define TI113X_SCR_SUBSYSRW 0x00000020
53 #define TI113X_SCR_CB_DPAR 0x00000010
54 #define TI113X_SCR_CDMA_EN 0x00000008
55 #define TI113X_SCR_ASYNC_IRQ 0x00000004
56 #define TI113X_SCR_KEEPCLK 0x00000002
57 #define TI113X_SCR_CLKRUN_ENA 0x00000001
59 #define TI122X_SCR_SER_STEP 0xc0000000
60 #define TI122X_SCR_INTRTIE 0x20000000
61 #define TIXX21_SCR_TIEALL 0x10000000
62 #define TI122X_SCR_CBRSVD 0x00400000
63 #define TI122X_SCR_MRBURSTDN 0x00008000
64 #define TI122X_SCR_MRBURSTUP 0x00004000
65 #define TI122X_SCR_RIMUX 0x00000001
68 #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
69 #define TI1250_MMC_ZVOUTEN 0x80
70 #define TI1250_MMC_PORTSEL 0x40
71 #define TI1250_MMC_ZVEN1 0x02
72 #define TI1250_MMC_ZVEN0 0x01
74 #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
75 #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
76 #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
77 #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
78 #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
79 #define TI1250_GPIO_MODE_MASK 0xc0
82 #define TI122X_MFUNC 0x008c /* 32 bit */
83 #define TI122X_MFUNC0_MASK 0x0000000f
84 #define TI122X_MFUNC1_MASK 0x000000f0
85 #define TI122X_MFUNC2_MASK 0x00000f00
86 #define TI122X_MFUNC3_MASK 0x0000f000
87 #define TI122X_MFUNC4_MASK 0x000f0000
88 #define TI122X_MFUNC5_MASK 0x00f00000
89 #define TI122X_MFUNC6_MASK 0x0f000000
91 #define TI122X_MFUNC0_INTA 0x00000002
92 #define TI125X_MFUNC0_INTB 0x00000001
93 #define TI122X_MFUNC1_INTB 0x00000020
94 #define TI122X_MFUNC3_IRQSER 0x00001000
98 #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
99 #define TI113X_RSR_PCIRETRY 0x80
100 #define TI113X_RSR_CBRETRY 0x40
101 #define TI113X_RSR_TEXP_CBB 0x20
102 #define TI113X_RSR_MEXP_CBB 0x10
103 #define TI113X_RSR_TEXP_CBA 0x08
104 #define TI113X_RSR_MEXP_CBA 0x04
105 #define TI113X_RSR_TEXP_PCI 0x02
106 #define TI113X_RSR_MEXP_PCI 0x01
109 #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
110 #define TI113X_CCR_RIENB 0x80
111 #define TI113X_CCR_ZVENABLE 0x40
112 #define TI113X_CCR_PCI_IRQ_ENA 0x20
113 #define TI113X_CCR_PCI_IREQ 0x10
114 #define TI113X_CCR_PCI_CSC 0x08
115 #define TI113X_CCR_SPKROUTEN 0x02
116 #define TI113X_CCR_IFG 0x01
118 #define TI1220_CCR_PORT_SEL 0x20
119 #define TI122X_CCR_AUD2MUX 0x04
122 #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
123 #define TI113X_DCR_5V_FORCE 0x40
124 #define TI113X_DCR_3V_FORCE 0x20
125 #define TI113X_DCR_IMODE_MASK 0x06
126 #define TI113X_DCR_IMODE_ISA 0x02
127 #define TI113X_DCR_IMODE_SERIAL 0x04
129 #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
130 #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
133 #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
134 #define TI113X_BCR_CB_READ_DEPTH 0x08
135 #define TI113X_BCR_CB_WRITE_DEPTH 0x04
136 #define TI113X_BCR_PCI_READ_DEPTH 0x02
137 #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
140 #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
141 #define TI1250_DIAG_TRUE_VALUE 0x80
142 #define TI1250_DIAG_PCI_IREQ 0x40
143 #define TI1250_DIAG_PCI_CSC 0x20
144 #define TI1250_DIAG_ASYNC_CSC 0x01
147 #define TI113X_DMA_0 0x0094 /* 32 bit */
148 #define TI113X_DMA_1 0x0098 /* 32 bit */
151 #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
154 #define ENE_TEST_C9 0xc9 /* 8bit */
155 #define ENE_TEST_C9_TLTENABLE 0x02
156 #define ENE_TEST_C9_PFENABLE_F0 0x04
157 #define ENE_TEST_C9_PFENABLE_F1 0x08
159 #define ENE_TEST_C9_WPDISALBLE_F0 0x40
160 #define ENE_TEST_C9_WPDISALBLE_F1 0x80
166 #define ti_sysctl(socket) ((socket)->private[0])
232 int shift = 0; in ti1250_zoom_video()
303 return 0; in ti_init()
316 return 0; in ti_override()
323 u32 isa_irq_mask = 0; in ti113x_use_isa_irq()
375 dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n", in ti12xx_irqroute_func0()
381 /* test PCI interrupts first. only try fixing if return value is 0! */ in ti12xx_irqroute_func0()
452 gpio3 = gpio3_old = 0; in ti12xx_irqroute_func0()
474 socket->cb_irq = 0; in ti12xx_irqroute_func0()
487 func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07); in ti12xx_align_irqs()
489 return 0; in ti12xx_align_irqs()
502 * the function 0 device. call from func1 only.
503 * returns 1 if INTRTIE changed, 0 otherwise.
512 return 0; in ti12xx_tie_interrupts()
517 return 0; in ti12xx_tie_interrupts()
548 dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n", in ti12xx_irqroute_func1()
559 /* test PCI interrupts first. only try fixing if return value is 0! */ in ti12xx_irqroute_func1()
643 socket->cb_irq = 0; in ti12xx_irqroute_func1()
696 return 0; in ti12xx_2nd_slot_empty()
706 devfn = socket->dev->devfn & ~0x07; in ti12xx_2nd_slot_empty()
708 (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01); in ti12xx_2nd_slot_empty()
728 ret = 0; in ti12xx_2nd_slot_empty()
752 return 0; in ti12xx_power_hook()
785 return 0; in ti12xx_power_hook()
789 if ((PCI_FUNC(socket->dev->devfn) == 0) || in ti12xx_power_hook()
801 gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40; in ti12xx_power_hook()
839 return 0; in ti12xx_power_hook()
848 if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) { in ti12xx_override()
871 if (PCI_FUNC(socket->dev->devfn) == 0) in ti12xx_override()
928 DEVID(PCI_VENDOR_ID_MOTOROLA, 0x1801, 0xECC0, PCI_ANY_ID,
930 DEVID(PCI_VENDOR_ID_MOTOROLA, 0x3410, 0xECC0, PCI_ANY_ID,
951 mask = (id->driver_data >> 8) & 0xFF; in ene_tune_bridge()
952 bits = id->driver_data & 0xFF; in ene_tune_bridge()
961 "EnE: changing testregister 0xC9, %02x -> %02x\n", in ene_tune_bridge()