Lines Matching +full:0 +full:x8c20
45 if (ret < 0) in pcie_lbms_seen()
48 return count > 0; in pcie_lbms_seen()
96 * Return 0 if the link has been successfully retrained. Return an error
102 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
270 u8 cls = 0; in pci_apply_final_quirks()
304 return 0; in pci_apply_final_quirks()
342 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
346 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
392 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
393 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
396 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
398 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
407 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { in quirk_nopcipci()
418 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
419 if (rev == 0x13) { in quirk_nopciamd()
430 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { in quirk_triton()
463 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
467 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
475 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
491 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
494 * Set bit 4 and bit 5 of byte 76 to 0x01 in quirk_vialatency()
499 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
515 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { in quirk_viaetbf()
524 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { in quirk_vsfx()
533 * space. Latency must be set to 0xA and Triton workaround applied too.
538 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { in quirk_alimagik()
549 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { in quirk_natoma()
562 * This chip can cause PCI parity errors if config register 0xA0 is read
567 dev->cfg_size = 0xA0; in quirk_citrine()
572 * This chip can cause bus lockups if config addresses above 0x600
577 dev->cfg_size = 0x600; in quirk_nfp6000()
589 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in quirk_extend_bar_to_page()
594 resource_set_range(r, 0, PAGE_SIZE); in quirk_extend_bar_to_page()
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
609 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
613 resource_set_range(r, 0, SZ_64M); in quirk_s3_64M()
659 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
660 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
702 * between 0x3b0->0x3bb or read 0x3d3
706 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
708 request_region(0x3b0, 0x0C, "RadeonIGP"); in quirk_ati_exploding_mce()
709 request_region(0x3d3, 0x01, "RadeonIGP"); in quirk_ati_exploding_mce()
715 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
720 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
763 PCI_CLASS_SERIAL_USB_XHCI, 0,
773 * 0xE0 (64 bytes of ACPI registers)
774 * 0xE2 (32 bytes of SMB registers)
778 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
779 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
792 base = devres & 0xffff; in piix4_io_quirk()
802 * reserve it (at least if it's in the 0x1000+ range), but in piix4_io_quirk()
817 base = devres & 0xffff0000; in piix4_mem_quirk()
818 mask = (devres & 0x3f) << 16; in piix4_mem_quirk()
837 * 0x40 (64 bytes of ACPI registers)
838 * 0x90 (16 bytes of SMB registers)
845 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
846 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
849 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
851 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
852 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
858 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
859 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
863 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
864 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
866 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
867 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
872 #define ICH_PMBASE 0x40
873 #define ICH_ACPI_CNTL 0x44
874 #define ICH4_ACPI_EN 0x10
875 #define ICH6_ACPI_EN 0x80
876 #define ICH4_GPIOBASE 0x58
877 #define ICH4_GPIO_CNTL 0x5c
878 #define ICH4_GPIO_EN 0x10
879 #define ICH6_GPIOBASE 0x48
880 #define ICH6_GPIO_CNTL 0x4c
881 #define ICH6_GPIO_EN 0x10
885 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
886 * 0x58 (64 bytes of GPIO I/O space)
946 base = val & 0xfffc; in ich6_lpc_generic_decode()
973 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
974 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
992 base = val & 0xfffc; in ich7_lpc_generic_decode()
993 mask = (val >> 16) & 0xfc; in ich7_lpc_generic_decode()
1010 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
1011 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
1012 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
1013 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
1031 * 0x48 or 0x20 (256 bytes of ACPI registers)
1035 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1036 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
1043 * 0x48 (256 bytes of ACPI registers)
1044 * 0x70 (128 bytes of hardware monitoring register)
1045 * 0x90 (16 bytes of SMB registers)
1051 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
1054 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
1060 * 0x88 (128 bytes of power management registers)
1061 * 0xd0 (16 bytes of SMB registers)
1065 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
1066 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
1105 tmp = 0; /* nothing routed to external APIC */ in quirk_via_ioapic()
1107 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1112 /* Offset 0x58: External APIC IRQ output control */ in quirk_via_ioapic()
1113 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
1129 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
1132 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
1149 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1162 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1174 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1193 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1194 pci_read_config_byte(d, 0x42, &irq); in quirk_via_acpi()
1195 irq &= 0xf; in quirk_via_acpi()
1268 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1293 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
1306 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
1323 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
1327 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
1328 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
1330 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1348 resource_set_range(r, 0, SZ_16M); in quirk_dunord()
1355 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1374 pci_read_config_byte(dev, 0x41, ®); in quirk_mediagx_master()
1377 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1379 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1394 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1396 pci_read_config_word(pdev, 0x40, &config); in quirk_disable_pxb()
1399 pci_write_config_word(pdev, 0x40, config); in quirk_disable_pxb()
1412 if (tmp == 0x01) { in quirk_amd_ide_mode()
1413 pci_read_config_byte(pdev, 0x40, &tmp); in quirk_amd_ide_mode()
1414 pci_write_config_byte(pdev, 0x40, tmp|1); in quirk_amd_ide_mode()
1415 pci_write_config_byte(pdev, 0x9, 1); in quirk_amd_ide_mode()
1416 pci_write_config_byte(pdev, 0xa, 6); in quirk_amd_ide_mode()
1417 pci_write_config_byte(pdev, 0x40, tmp); in quirk_amd_ide_mode()
1429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1430 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1495 * package 2.7.0 for details)
1522 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1523 case 0x8070: /* P4B */ in asus_hides_smbus_hostbridge()
1524 case 0x8088: /* P4B533 */ in asus_hides_smbus_hostbridge()
1525 case 0x1626: /* L3C notebook */ in asus_hides_smbus_hostbridge()
1530 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1531 case 0x80b2: /* P4PE */ in asus_hides_smbus_hostbridge()
1532 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1537 case 0x8030: /* P4T533 */ in asus_hides_smbus_hostbridge()
1542 case 0x8070: /* P4G8X Deluxe */ in asus_hides_smbus_hostbridge()
1547 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1552 case 0x1751: /* M2N notebook */ in asus_hides_smbus_hostbridge()
1553 case 0x1821: /* M5N notebook */ in asus_hides_smbus_hostbridge()
1554 case 0x1897: /* A6L notebook */ in asus_hides_smbus_hostbridge()
1559 case 0x184b: /* W1N notebook */ in asus_hides_smbus_hostbridge()
1560 case 0x186a: /* M6Ne notebook */ in asus_hides_smbus_hostbridge()
1565 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1570 case 0x1882: /* M6V notebook */ in asus_hides_smbus_hostbridge()
1571 case 0x1977: /* A6VA notebook */ in asus_hides_smbus_hostbridge()
1577 case 0x088C: /* HP Compaq nc8000 */ in asus_hides_smbus_hostbridge()
1578 case 0x0890: /* HP Compaq nc6000 */ in asus_hides_smbus_hostbridge()
1583 case 0x12bc: /* HP D330L */ in asus_hides_smbus_hostbridge()
1584 case 0x12bd: /* HP D530 */ in asus_hides_smbus_hostbridge()
1585 case 0x006a: /* HP Compaq nx9500 */ in asus_hides_smbus_hostbridge()
1590 case 0x12bf: /* HP xw4100 */ in asus_hides_smbus_hostbridge()
1596 case 0xC00C: /* Samsung P35 notebook */ in asus_hides_smbus_hostbridge()
1602 case 0x0058: /* Compaq Evo N620c */ in asus_hides_smbus_hostbridge()
1607 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1615 case 0x00b8: /* Compaq Evo D510 CMT */ in asus_hides_smbus_hostbridge()
1616 case 0x00b9: /* Compaq Evo D510 SFF */ in asus_hides_smbus_hostbridge()
1617 case 0x00ba: /* Compaq Evo D510 USDT */ in asus_hides_smbus_hostbridge()
1627 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ in asus_hides_smbus_hostbridge()
1657 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1658 if (val & 0x8) { in asus_hides_smbus_lpc()
1659 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1660 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1661 if (val & 0x8) in asus_hides_smbus_lpc()
1662 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1693 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1695 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); in asus_hides_smbus_lpc_ich6_suspend()
1708 val = readl(asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1711 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1738 u8 val = 0; in quirk_sis_96x_smbus()
1739 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1740 if (val & 0x10) { in quirk_sis_96x_smbus()
1742 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1762 #define SIS_DETECT_REGISTER 0x40
1772 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { in quirk_sis_503()
1797 int asus_hides_ac97 = 0; in asus_hides_ac97_lpc()
1807 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1808 if (val & 0xc0) { in asus_hides_ac97_lpc()
1809 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1810 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1811 if (val & 0xc0) in asus_hides_ac97_lpc()
1812 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1832 /* Only poke fn 0 */ in quirk_jmicron_ata()
1836 pci_read_config_dword(pdev, 0x40, &conf1); in quirk_jmicron_ata()
1837 pci_read_config_dword(pdev, 0x80, &conf5); in quirk_jmicron_ata()
1839 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1847 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ in quirk_jmicron_ata()
1858 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ in quirk_jmicron_ata()
1859 /* Set the class codes correctly and then direct IDE 0 */ in quirk_jmicron_ata()
1860 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ in quirk_jmicron_ata()
1865 conf1 |= 0x00C00000; /* Set 22, 23 */ in quirk_jmicron_ata()
1869 pci_write_config_dword(pdev, 0x40, conf1); in quirk_jmicron_ata()
1870 pci_write_config_dword(pdev, 0x80, conf5); in quirk_jmicron_ata()
1909 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, qu…
1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1918 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1926 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) in quirk_alder_ioapic()
1927 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1934 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1959 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch…
1980 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1998 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
2059 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
2092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
2100 return 0; in dmi_disable_ioapicreroute()
2170 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2173 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2192 case 0x3c28: /* Xeon E5 1600/2600/4600 */ in quirk_disable_intel_boot_interrupt()
2193 case 0x0e28: /* Xeon E5/E7 V2 */ in quirk_disable_intel_boot_interrupt()
2194 case 0x2f28: /* Xeon E5/E7 V3,V4 */ in quirk_disable_intel_boot_interrupt()
2195 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2196 case 0x2034: /* Xeon Scalable Family */ in quirk_disable_intel_boot_interrupt()
2219 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2235 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2241 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2243 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2247 #define BC_HT1000_FEATURE_REG 0x64
2248 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2249 #define BC_HT1000_MAP_IDX 0xC00
2250 #define BC_HT1000_MAP_DATA 0xC01
2264 for (irq = 0x10; irq < 0x10 + 32; irq++) { in quirk_disable_broadcom_boot_interrupt()
2266 outb(0x00, BC_HT1000_MAP_DATA); in quirk_disable_broadcom_boot_interrupt()
2284 #define AMD_813X_MISC 0x40
2285 #define AMD_813X_NOIOAMODE (1<<0)
2286 #define AMD_813X_REV_B1 0x12
2287 #define AMD_813X_REV_B2 0x13
2311 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2326 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
2341 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2343 if (r->start & 0x8) { in quirk_tc86c001_ide()
2345 resource_set_range(r, 0, SZ_16); in quirk_tc86c001_ide()
2356 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2366 for (bar = 0; bar <= 1; bar++) in quirk_plx_pci9050()
2367 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
2368 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
2373 resource_set_range(r, 0, SZ_256); in quirk_plx_pci9050()
2379 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2380 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2381 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2382 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2384 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2387 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2388 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2392 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2393 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2402 * The subdevice ID is of the form 0x00PS, where <P> is the number in quirk_netmos()
2409 dev->subsystem_device == 0x0299) in quirk_netmos()
2420 (dev->class & 0xff); in quirk_netmos()
2435 case 0x1029: in quirk_e100_interrupt()
2436 case 0x1030 ... 0x1034: in quirk_e100_interrupt()
2437 case 0x1038 ... 0x103E: in quirk_e100_interrupt()
2438 case 0x1050 ... 0x1057: in quirk_e100_interrupt()
2439 case 0x1059: in quirk_e100_interrupt()
2440 case 0x1064 ... 0x106B: in quirk_e100_interrupt()
2441 case 0x1091 ... 0x1095: in quirk_e100_interrupt()
2442 case 0x1209: in quirk_e100_interrupt()
2443 case 0x1229: in quirk_e100_interrupt()
2444 case 0x2449: in quirk_e100_interrupt()
2445 case 0x2459: in quirk_e100_interrupt()
2446 case 0x245D: in quirk_e100_interrupt()
2447 case 0x27DC: in quirk_e100_interrupt()
2462 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
2476 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
2483 if (cmd_hi == 0) { in quirk_e100_interrupt()
2502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2507 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2510 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2512 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2569 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2571 if (en1k & 0x200) { in quirk_p64h2_1k_io()
2576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2587 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2588 if (!(b & 0x20)) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2589 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2604 * bus leading to USB2.0 packet loss. in quirk_via_cx700_pci_parking_caching()
2625 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2626 if (b & 0x40) { in quirk_via_cx700_pci_parking_caching()
2628 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2634 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2635 if (b != 0) { in quirk_via_cx700_pci_parking_caching()
2637 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2640 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2643 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2655 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2658 if (rev == 0x05719000) { in quirk_brcm_5719_limit_mrrs()
2678 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2680 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2733 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2735 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2756 &flags) == 0) { in msi_ht_cap_enabled()
2760 return (flags & HT_MSI_FLAGS_ENABLE) != 0; in msi_ht_cap_enabled()
2766 return 0; in msi_ht_cap_enabled()
2790 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2810 &flags) == 0) { in ht_enable_msi_mapping()
2847 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2859 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2862 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2865 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2868 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2871 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2874 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2877 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2880 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2883 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2886 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2889 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2892 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2895 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2898 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2901 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2904 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2925 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2930 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2943 int found = 0; in ht_check_msi_mapping()
2953 &flags) == 0) { in ht_check_msi_mapping()
2973 int found = 0; in host_bridge_with_leaf()
2976 for (i = dev_no + 1; i < 0x20; i++) { in host_bridge_with_leaf()
2977 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2983 if (pos != 0) { in host_bridge_with_leaf()
3005 int end = 0; in is_end_of_ht_chain()
3031 int found = 0; in nv_ht_enable_msi_mapping()
3034 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
3035 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3040 if (pos != 0) { in nv_ht_enable_msi_mapping()
3074 &flags) == 0) { in ht_disable_msi_mapping()
3098 if (found == 0) in __nv_msi_ht_cap_quirk()
3105 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3106 PCI_DEVFN(0, 0)); in __nv_msi_ht_cap_quirk()
3113 if (pos != 0) { in __nv_msi_ht_cap_quirk()
3145 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
3169 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3176 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ in quirk_msi_intx_disable_qca_bug()
3177 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3257 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3292 * live on PCI function 0, which might be the CardBus controller or the
3309 * This must be done via function #0 in ricoh_mmc_fixup_rl5c476()
3314 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
3315 if (disable & 0x02) in ricoh_mmc_fixup_rl5c476()
3318 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
3319 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
3320 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
3321 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
3322 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
3323 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
3324 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
3340 * This must be done via function #0 in ricoh_mmc_fixup_r5c832()
3345 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize in ricoh_mmc_fixup_r5c832()
3349 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3351 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3352 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3353 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3354 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3358 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
3359 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
3360 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
3361 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
3362 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
3363 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
3368 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
3370 if (disable & 0x02) in ricoh_mmc_fixup_r5c832()
3373 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
3374 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
3375 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
3376 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
3391 #define VTUNCERRMSK_REG 0x1ac
3410 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3423 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3440 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3464 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
3475 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3521 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
3527 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
3533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3548 #define I915_DEIER_REG 0x4400c
3551 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3558 if (readl(regs + I915_DEIER_REG) != 0) { in disable_igfx_irq()
3561 writel(0, regs + I915_DEIER_REG); in disable_igfx_irq()
3566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3580 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3620 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3622 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3693 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { in mellanox_check_broken_intx_masking()
3717 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); in mellanox_check_broken_intx_masking()
3726 fw_major = fw_maj_min & 0xffff; in mellanox_check_broken_intx_masking()
3728 fw_subminor = fw_sub_min & 0xffff; in mellanox_check_broken_intx_masking()
3756 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3903 acpi_execute_simple_method(SXFP, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3905 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3906 acpi_execute_simple_method(SXIO, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3907 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3931 return 0; in reset_intel_82599_sfp_virtfn()
3934 #define SOUTH_CHICKEN2 0xc2004
3935 #define PCH_PP_STATUS 0xc7200
3936 #define PCH_PP_CONTROL 0xc7204
3937 #define MSG_CTL 0x45010
3938 #define NSDE_PWR_STATE 0xd0100
3948 return 0; in reset_ivb_igd()
3950 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3954 iowrite32(0x00000002, mmio_base + MSG_CTL); in reset_ivb_igd()
3962 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); in reset_ivb_igd()
3964 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; in reset_ivb_igd()
3970 if ((val & 0xb0000000) == 0) in reset_ivb_igd()
3977 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); in reset_ivb_igd()
3980 return 0; in reset_ivb_igd()
3993 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3997 * If this is the "probe" phase, return 0 indicating that we can in reset_chelsio_generic_dev()
4001 return 0; in reset_chelsio_generic_dev()
4027 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) in reset_chelsio_generic_dev()
4042 return 0; in reset_chelsio_generic_dev()
4045 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
4046 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
4047 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
4069 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) in nvme_disable_and_flr()
4073 return 0; in nvme_disable_and_flr()
4075 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); in nvme_disable_and_flr()
4127 return 0; in nvme_disable_and_flr()
4146 return 0; in delay_250ms_after_flr()
4149 #define PCI_DEVICE_ID_HINIC_VF 0x375E
4150 #define HINIC_VF_FLR_TYPE 0x1000
4152 #define HINIC_VF_OP 0xE80
4164 return 0; in reset_hinic_vf_dev()
4166 bar = pci_iomap(pdev, 0, 0); in reset_hinic_vf_dev()
4189 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); in reset_hinic_vf_dev()
4209 return 0; in reset_hinic_vf_dev()
4219 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4220 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4221 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4222 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
4227 { 0 }
4252 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4253 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4259 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4264 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */
4265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias);
4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias);
4280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4329 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4330 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4341 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4349 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4350 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4351 .driver_data = PCI_DEVFN(1, 0) },
4352 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4353 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4354 .driver_data = PCI_DEVFN(1, 0) },
4355 { 0 }
4366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4389 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4391 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4393 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4395 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4405 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); in quirk_mic_x200_dma_alias()
4406 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); in quirk_mic_x200_dma_alias()
4407 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); in quirk_mic_x200_dma_alias()
4409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4421 * All possible slot numbers (0x20) are used, since we are unable to tell
4428 const unsigned int num_pci_slots = 0x20; in quirk_pex_vca_alias()
4431 for (slot = 0; slot < num_pci_slots; slot++) in quirk_pex_vca_alias()
4432 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); in quirk_pex_vca_alias()
4434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4464 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4468 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4470 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4472 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4474 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4493 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4495 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4497 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4499 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4501 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4503 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4505 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4507 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4509 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4511 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4513 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4515 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4517 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4519 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4521 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4523 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4525 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4527 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4529 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4531 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4533 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4535 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4537 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4539 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4541 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4543 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4545 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4547 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4559 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4561 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4563 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4567 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4614 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4615 * 0x54xx so we use that one. in quirk_chelsio_T5_disable_root_port_attributes()
4617 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4632 * caller desires. Return 0 otherwise.
4638 return 0; in pci_acs_ctrl_enabled()
4677 status = acpi_get_table("IVRS", 0, &header); in pci_quirk_amd_sb_acs()
4702 case 0xa000 ... 0xa7ff: /* ThunderX1 */ in pci_quirk_cavium_acs_match()
4703 case 0xaf84: /* ThunderX2 */ in pci_quirk_cavium_acs_match()
4704 case 0xb884: /* ThunderX3 */ in pci_quirk_cavium_acs_match()
4756 case 0x0710 ... 0x071e: in pci_quirk_zhaoxin_pcie_ports_acs()
4757 case 0x0721: in pci_quirk_zhaoxin_pcie_ports_acs()
4758 case 0x0723 ... 0x0752: in pci_quirk_zhaoxin_pcie_ports_acs()
4774 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4775 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4777 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4778 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4780 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4781 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4783 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4784 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4786 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4787 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4789 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4790 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4792 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4794 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4795 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4797 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4808 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) in pci_quirk_intel_pch_acs_match()
4824 return pci_acs_ctrl_enabled(acs_flags, 0); in pci_quirk_intel_pch_acs()
4870 return acs_flags ? 0 : 1; in pci_quirk_al_acs()
4883 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4884 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4896 * 0xa290-0xa29f PCI Express Root port #{0-16}
4897 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4908 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4924 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ in pci_quirk_intel_spt_pch_acs_match()
4925 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ in pci_quirk_intel_spt_pch_acs_match()
4926 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ in pci_quirk_intel_spt_pch_acs_match()
5010 case 0x0100 ... 0x010F: /* EM */ in pci_quirk_wangxun_nic_acs()
5011 case 0x1001: case 0x2001: /* SP */ in pci_quirk_wangxun_nic_acs()
5012 case 0x5010: case 0x5025: case 0x5040: /* AML */ in pci_quirk_wangxun_nic_acs()
5013 case 0x5110: case 0x5125: case 0x5140: /* AML */ in pci_quirk_wangxun_nic_acs()
5026 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
5027 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
5028 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
5029 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
5030 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
5031 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
5032 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
5033 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
5034 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
5035 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
5036 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
5037 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
5038 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
5039 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
5040 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
5041 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
5042 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
5043 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
5044 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
5045 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
5046 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
5047 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
5048 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
5049 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
5050 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
5051 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
5052 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
5053 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
5054 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
5055 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
5056 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
5058 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
5059 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
5060 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
5061 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
5062 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
5063 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
5064 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
5066 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
5067 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
5068 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
5069 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
5070 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
5071 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
5072 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
5073 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
5075 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
5076 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
5077 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
5079 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
5080 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
5081 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
5082 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
5084 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
5085 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
5086 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
5087 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
5089 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
5090 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
5093 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
5094 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
5096 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs },
5098 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
5102 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5103 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5107 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
5108 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
5109 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
5111 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
5113 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
5114 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
5115 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
5116 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
5117 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
5118 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
5119 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
5120 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
5122 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
5123 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
5124 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
5125 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
5126 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs },
5127 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs },
5128 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs },
5129 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs },
5130 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
5132 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
5134 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
5135 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
5136 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
5139 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
5140 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
5141 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
5143 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
5144 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
5145 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
5147 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
5148 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
5149 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
5151 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
5152 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
5153 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
5155 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5156 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5157 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5159 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5160 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5161 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5163 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5164 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5165 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5167 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5168 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5169 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5174 { 0 }
5185 * 0: Device does not provide all the desired controls
5186 * >0: Device provides all the controls in @acs_flags
5205 if (ret >= 0) in pci_dev_specific_acs_enabled()
5214 #define INTEL_LPC_RCBA_REG 0xf0
5216 #define INTEL_LPC_RCBA_MASK 0xffffc000
5218 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5221 #define INTEL_BSPR_REG 0x1104
5228 #define INTEL_UPDCR_REG 0x1014
5229 /* 5:0 Peer Decode Enable bits */
5230 #define INTEL_UPDCR_REG_MASK 0x3f
5242 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5271 return 0; in pci_quirk_enable_intel_lpc_acs()
5275 #define INTEL_MPC_REG 0xd8
5311 return 0; in pci_quirk_enable_intel_pch_acs()
5320 return 0; in pci_quirk_enable_intel_pch_acs()
5350 return 0; in pci_quirk_enable_intel_spt_pch_acs()
5374 return 0; in pci_quirk_disable_intel_spt_pch_acs_redir()
5397 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_enable_acs()
5405 if (ret >= 0) in pci_dev_specific_enable_acs()
5418 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_disable_acs_redir()
5426 if (ret >= 0) in pci_dev_specific_disable_acs_redir()
5435 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5438 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5443 int pos, i = 0, ret; in quirk_intel_qat_vf_cap()
5459 * is not the expected incorrect 0x00. in quirk_intel_qat_vf_cap()
5466 * PCIe Capability Structure is expected to be at 0x50 and should in quirk_intel_qat_vf_cap()
5467 * terminate the list (Next Capability pointer is 0x00). Verify in quirk_intel_qat_vf_cap()
5473 pos = 0x50; in quirk_intel_qat_vf_cap()
5475 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { in quirk_intel_qat_vf_cap()
5502 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5504 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5515 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5520 * AMD Starship/Matisse HD Audio Controller 0x1487
5521 * AMD Starship USB 3.0 Host Controller 0x148c
5522 * AMD Matisse USB 3.0 Host Controller 0x149c
5523 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5524 * Intel 82579V Gigabit Ethernet Controller 0x1503
5531 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5532 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5533 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5534 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5535 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5536 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5537 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr);
5539 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
5542 if (dev->revision == 0x1) in quirk_no_flr_snet()
5545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
5560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5572 pdev->ats_cap = 0; in quirk_no_ats()
5582 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5583 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5584 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5585 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5586 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5587 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5621 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5686 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_hda()
5701 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb()
5714 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5717 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb_typec_ucsi()
5739 /* Bit 25 at offset 0x488 enables the HDA controller */ in quirk_nvidia_hda()
5740 pci_read_config_dword(gpu, 0x488, &val); in quirk_nvidia_hda()
5745 pci_write_config_dword(gpu, 0x488, val | BIT(25)); in quirk_nvidia_hda()
5758 * completions for config read requests even though PCIe r4.0, sec
5771 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5784 u16 ctrl = 0; in pci_idt_bus_quirk()
5802 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); in pci_idt_bus_quirk()
5832 mmio = pci_iomap(pdev, 0, 0); in quirk_switchtec_ntb_dma_alias()
5850 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { in quirk_switchtec_ntb_dma_alias()
5852 u32 table_sz = 0; in quirk_switchtec_ntb_dma_alias()
5864 pci_warn(pdev, "Partition %d table_sz 0\n", pp); in quirk_switchtec_ntb_dma_alias()
5875 for (te = 0; te < table_sz; te++) { in quirk_switchtec_ntb_dma_alias()
5880 devfn = (rid_entry >> 1) & 0xFF; in quirk_switchtec_ntb_dma_alias()
5895 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5896 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5897 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5898 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5899 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5900 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5901 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5902 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5903 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5904 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5905 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5906 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5907 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5908 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5909 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5910 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5911 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5912 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5913 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5914 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5915 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5916 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5917 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5918 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5919 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5920 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5921 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5922 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5923 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5924 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5925 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5926 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5927 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5928 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5929 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5930 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5931 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5932 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5933 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5934 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5935 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5936 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5937 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5938 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5939 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5940 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5941 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5942 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5943 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5944 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5945 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5946 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5947 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5948 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5949 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5950 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5951 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5952 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */
5953 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */
5954 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */
5955 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */
5956 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */
5957 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */
5958 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */
5959 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */
5960 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */
5961 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */
5962 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */
5963 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */
5964 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */
5965 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */
5966 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */
5967 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */
5968 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */
5969 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */
5970 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */
5971 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */
5972 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */
5973 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */
5974 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */
5975 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */
5976 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */
5977 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */
5978 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */
5979 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */
5980 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */
5981 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */
5982 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */
5983 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */
5984 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */
5985 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */
5986 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */
5987 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */
5992 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */
5993 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */
5994 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */
5995 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */
5996 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */
5997 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */
6010 pci_add_dma_alias(pdev, 0, 256); in quirk_plx_ntb_dma_alias()
6012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
6013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
6037 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6048 map = pci_iomap(pdev, 0, 0x23000); in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6058 if (ioread32(map + 0x2240c) & 0x2) { in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6061 if (ret < 0) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6069 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
6082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
6085 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
6101 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
6104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
6110 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
6122 #define PI7C9X2Gxxx_MODE_REG 0x74
6123 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
6155 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
6157 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
6159 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
6161 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
6163 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
6165 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
6172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
6179 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
6180 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
6181 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
6182 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
6198 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", in aspm_l1_acceptable_latency()
6202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
6203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
6204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
6205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
6206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
6207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
6208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
6209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
6210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
6211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
6212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
6213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
6214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
6215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
6216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
6217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
6218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
6219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
6220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
6221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
6222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
6223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
6224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
6225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6248 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { in dpc_log_size()
6254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size);
6271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size);
6272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
6283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
6284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
6298 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);
6316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);
6317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);