91 	 * Upstream Port below it.  in pci_save_aspm_l1ss_state()
134 	 * on the downstream component before the upstream. So, don't attempt to  in pci_restore_aspm_l1ss_state()
168 	 * by the upstream  in pci_restore_aspm_l1ss_state()
215 #define PCIE_LINK_STATE_L0S_UP	BIT(0)	/* Upstream direction L0s state */
228 	struct pci_dev *pdev;		/* Upstream component of the Link */
425 	/* Check upstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
458 	/* Configure upstream component */  in pcie_aspm_configure_common_clock()
602 		/* Check upstream direction L0s latency */  in pcie_aspm_check_latency()
710 	/* Program Common_Mode_Restore_Time in upstream device */  in aspm_calc_l12_info()
818 	 * Re-read upstream/downstream components' register state after  in pcie_aspm_cap_init()
929 	u32 upstream = 0, dwstream = 0;  in pcie_config_aspm_link()  local
949 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
953 		upstream |= PCI_EXP_LNKCTL_ASPM_L0S;  in pcie_config_aspm_link()
955 		upstream |= PCI_EXP_LNKCTL_ASPM_L1;  in pcie_config_aspm_link()
967 	 * Upstream component, and ASPM L1 must be enabled in the Upstream  in pcie_config_aspm_link()
980 	pcie_config_aspm_dev(parent, upstream);  in pcie_config_aspm_link()
1108 	 * We allocate pcie_link_state for the component on the upstream  in pcie_aspm_init_link_state()
1130 	 * upstream links also because capable state of them can be  in pcie_aspm_init_link_state()
1220 	 * disabled in the upstream bridge, so re-enable it before enabling  in pci_configure_ltr()
1277 	 * switch upstream port, this link state is parent_link to all  in pcie_aspm_exit_link_state()
1287 	/* Recheck latencies and configure upstream links */  in pcie_aspm_exit_link_state()
1554  * Relies on the upstream bridge's link_state being valid.  The link_state