3  * Enable PCIe link L0s/L1 state and Clock Power Management
100 	 * Save L1 substate configuration. The ASPM L0s/L1 configuration  in pci_save_aspm_l1ss_state()
112 	 * Save parent's L1 substate configuration so we have it for  in pci_save_aspm_l1ss_state()
133 	 * In case BIOS enabled L1.2 when resuming, we need to disable it first  in pci_restore_aspm_l1ss_state()
155 	/* Make sure L0s/L1 are disabled before updating L1SS config */  in pci_restore_aspm_l1ss_state()
167 	 * Disable L1.2 on this downstream endpoint device first, followed  in pci_restore_aspm_l1ss_state()
177 	 * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2  in pci_restore_aspm_l1ss_state()
199 	/* Restore L0s/L1 if they were enabled */  in pci_restore_aspm_l1ss_state()
276  * The L1 PM substate capability is only implemented in function 0 in a
296 		/* Enable ASPM L0s/L1 */  in policy_to_aspm_state()
493 /* Convert L1 latency encoding to ns */
503 /* Convert L1 acceptable latency encoding to ns */
527  * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
528  * register.  Ports enter L1.2 when the most recent LTR value is greater
530  * don't enter L1.2 too aggressively.
585 	/* Calculate endpoint L1 acceptable latency */  in pcie_aspm_check_latency()
612 		 * Check L1 latency.  in pcie_aspm_check_latency()
614 		 * more microsecond for L1. Spec doesn't mention L0s.  in pcie_aspm_check_latency()
616 		 * The exit latencies for L1 substates are not advertised  in pcie_aspm_check_latency()
618 		 * to determine max latencies introduced by enabling L1  in pcie_aspm_check_latency()
620 		 * a L1 substate exit latency check.  We assume that the  in pcie_aspm_check_latency()
621 		 * L1 exit latencies advertised by a device include L1  in pcie_aspm_check_latency()
634 /* Calculate L1.2 PM substate timing parameters */
669 	 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if  in aspm_calc_l12_info()
674 	 * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at  in aspm_calc_l12_info()
683 	/* Some broken devices only support dword access to L1 SS */  in aspm_calc_l12_info()
693 	/* Disable L1.2 while updating.  See PCIe r5.0, sec 5.5.4, 7.8.3.3 */  in aspm_calc_l12_info()
743 	/* Setup L1 substate */  in aspm_l1ss_init()
756 	 * to this device, we can't use ASPM L1.2 because it relies on the  in aspm_l1ss_init()
819 	 * clock configuration.  L0s & L1 exit latencies in the otherwise  in pcie_aspm_cap_init()
828 	/* Disable L0s/L1 before updating L1SS config */  in pcie_aspm_cap_init()
852 	/* Setup L1 state */  in pcie_aspm_cap_init()
861 	/* Restore L0s/L1 if they were enabled */  in pcie_aspm_cap_init()
884 /* Configure the ASPM L1 substates. Caller must disable L1 first. */
901 	 * PCIe r6.2, sec 5.5.4, rules for enabling L1 PM Substates:  in pcie_config_aspm_l1ss()
902 	 * - Clear L1.x enable bits at child first, then at parent  in pcie_config_aspm_l1ss()
903 	 * - Set L1.x enable bits at parent first, then at child  in pcie_config_aspm_l1ss()
904 	 * - ASPM/PCIPM L1.2 must be disabled while programming timing  in pcie_config_aspm_l1ss()
908 	/* Disable all L1 substates */  in pcie_config_aspm_l1ss()
936 	/* Can't enable any substates if L1 is not enabled */  in pcie_config_aspm_link()
961 	 * bits for ASPM L1 PM Substates must be done while ASPM L1 is  in pcie_config_aspm_link()
962 	 * disabled. Disable L1 here and apply new configuration after L1SS  in pcie_config_aspm_link()
965 	 * Per sec 7.5.3.7, when disabling ASPM L1, software must disable  in pcie_config_aspm_link()
967 	 * Upstream component, and ASPM L1 must be enabled in the Upstream  in pcie_config_aspm_link()
1359 	/* L1 PM substates require L1 */  in pci_calc_aspm_disable_mask()
1370 	/* L1 PM substates require L1 */  in pci_calc_aspm_enable_mask()
1474  * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1493  * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1596 		/* need to enable L1 for substates */  in aspm_attr_store_common()
1624 ASPM_ATTR(l1_aspm, L1)  in ASPM_ATTR()