3  * Enable PCIe link L0s/L1 state and Clock Power Management
100 	 * Save L1 substate configuration. The ASPM L0s/L1 configuration  in pci_save_aspm_l1ss_state()
155 	/* Make sure L0s/L1 are disabled before updating L1SS config */  in pci_restore_aspm_l1ss_state()
199 	/* Restore L0s/L1 if they were enabled */  in pci_restore_aspm_l1ss_state()
215 #define PCIE_LINK_STATE_L0S_UP	BIT(0)	/* Upstream direction L0s state */
216 #define PCIE_LINK_STATE_L0S_DW	BIT(1)	/* Downstream direction L0s state */
296 		/* Enable ASPM L0s/L1 */  in policy_to_aspm_state()
475 /* Convert L0s latency encoding to ns */
485 /* Convert L0s acceptable latency encoding to ns */
581 	/* Calculate endpoint L0s acceptable latency */  in pcie_aspm_check_latency()
602 		/* Check upstream direction L0s latency */  in pcie_aspm_check_latency()
607 		/* Check downstream direction L0s latency */  in pcie_aspm_check_latency()
614 		 * more microsecond for L1. Spec doesn't mention L0s.  in pcie_aspm_check_latency()
819 	 * clock configuration.  L0s & L1 exit latencies in the otherwise  in pcie_aspm_cap_init()
828 	/* Disable L0s/L1 before updating L1SS config */  in pcie_aspm_cap_init()
838 	 * Setup L0s state  in pcie_aspm_cap_init()
840 	 * Note that we must not enable L0s in either direction on a  in pcie_aspm_cap_init()
842 	 * support L0s.  in pcie_aspm_cap_init()
861 	/* Restore L0s/L1 if they were enabled */  in pcie_aspm_cap_init()
1623 ASPM_ATTR(l0s_aspm, L0S)  in ASPM_ATTR()  argument