1 /* SPDX-License-Identifier: GPL-2.0 */
32  * "T_PERST-CLK".
37  * End of conventional reset (PERST# de-asserted) to first configuration
44  * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
52  * - "With a Downstream Port that does not support Link speeds greater
57  * - "With a Downstream Port that supports Link speeds greater than
167 	pm_wakeup_event(&dev->dev, 100);  in pci_wakeup_event()
171  * pci_bar_index_is_valid - Check whether a BAR index is within valid range
188 	return !!(pci_dev->subordinate);  in pci_has_subordinate()
197 	return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;  in pci_power_manageable()
259 	if (dev->bus->self)  in pci_no_d1d2()
260 		parent_dstates = dev->bus->self->no_d1d2;  in pci_no_d1d2()
261 	return (dev->no_d1d2 || parent_dstates);  in pci_no_d1d2()
287  * pci_match_one_device - Tell if a PCI device structure has a matching
297 	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&  in pci_match_one_device()
298 	    (id->device == PCI_ANY_ID || id->device == dev->device) &&  in pci_match_one_device()
299 	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&  in pci_match_one_device()
300 	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&  in pci_match_one_device()
301 	    !((id->class ^ dev->class) & id->class_mask))  in pci_match_one_device()
321 	pci_bar_mem32,		/* A 32-bit memory BAR */
322 	pci_bar_mem64,		/* A 64-bit memory BAR */
417 	return -EINVAL;  in pcie_dev_speed_mbps()
427 	bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];  in __pcie_update_link_speed()
435 	u32		cap;		/* SR-IOV Capabilities */
436 	u16		ctrl;		/* SR-IOV Control */
476  * pci_dev_set_io_state - Set the new error state if possible.
493 		xchg(&dev->error_state, pci_channel_io_perm_failure);  in pci_dev_set_io_state()
496 		old = cmpxchg(&dev->error_state, pci_channel_io_normal,  in pci_dev_set_io_state()
500 		old = cmpxchg(&dev->error_state, pci_channel_io_frozen,  in pci_dev_set_io_state()
525 	set_bit(PCI_DEV_ADDED, &dev->priv_flags);  in pci_dev_assign_added()
531 	return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags);  in pci_dev_test_and_clear_added()
536 	return test_bit(PCI_DEV_ADDED, &dev->priv_flags);  in pci_dev_is_added()
541 	return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags);  in pci_dev_test_and_set_removed()
656 	return -ENODEV;  in pci_iov_init()
700 	int resno = res - dev->resource;  in pci_resource_alignment()
705 	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)  in pci_resource_alignment()
720 	return -ENOTTY;  in pci_dev_specific_acs_enabled()
724 	return -ENOTTY;  in pci_dev_specific_enable_acs()
728 	return -ENOTTY;  in pci_dev_specific_disable_acs_redir()
732 	return -ENOTTY;  in pcie_failed_link_retrain()
741 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
744 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */
782 	return -EOPNOTSUPP;  in pcie_lbms_count()
803 	return -ENOTTY;  in pci_dev_specific_reset()
814 	return -ENODEV;  in acpi_get_rc_resources()
846 	return -1;  in of_get_pci_domain_nr()
852 	return -EINVAL;  in of_pci_get_max_link_speed()
915 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }  in pci_aer_clear_status()
916 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }  in pci_aer_raw_clear_status()
942 	return -ENOTTY;  in pci_dev_acpi_reset()
947 	return -ENODEV;  in pci_acpi_program_hp_params()
959 	return -ENODEV;  in acpi_pci_set_power_state()
968 	return -ENODEV;  in acpi_pci_wakeup()
995 	return -ENODEV;  in mid_pci_set_power_state()
1012  * Section 3.2.2.3.2, Figure 3-2, p. 50.
1040  * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
1042  * are used for specifying additional 4 high bits of PCI Express register.