1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "pcie-plda.h"
87 /* PCIe Config space MSI capability structure */
300 	struct plda_msi *msi = &port->plda.msi;  in mc_pcie_enable_msi()
315 	writel_relaxed(lower_32_bits(msi->vector_phy),  in mc_pcie_enable_msi()
317 	writel_relaxed(upper_32_bits(msi->vector_phy),  in mc_pcie_enable_msi()
328 	u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT);  in pcie_events()
340 	u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT);  in sec_errors()
352 	u32 reg = readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT);  in ded_errors()
364 	u32 reg = readl_relaxed(port->bridge_base_addr + ISTATUS_LOCAL);  in local_events()
390 	struct device *dev = port->dev;  in mc_event_handler()
393 	data = irq_domain_get_irq_data(port->event_domain, irq);  in mc_event_handler()
395 	if (event_cause[data->hwirq].str)  in mc_event_handler()
396 		dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);  in mc_event_handler()
398 		dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);  in mc_event_handler()
407 	u32 event = data->hwirq;  in mc_ack_event_irq()
412 		addr = mc_port->bridge_base_addr;  in mc_ack_event_irq()
414 		addr = mc_port->ctrl_base_addr;  in mc_ack_event_irq()
427 	u32 event = data->hwirq;  in mc_mask_event_irq()
433 		addr = mc_port->bridge_base_addr;  in mc_mask_event_irq()
435 		addr = mc_port->ctrl_base_addr;  in mc_mask_event_irq()
447 	raw_spin_lock(&port->lock);  in mc_mask_event_irq()
455 	raw_spin_unlock(&port->lock);  in mc_mask_event_irq()
462 	u32 event = data->hwirq;  in mc_unmask_event_irq()
468 		addr = mc_port->bridge_base_addr;  in mc_unmask_event_irq()
470 		addr = mc_port->ctrl_base_addr;  in mc_unmask_event_irq()
484 	raw_spin_lock(&port->lock);  in mc_unmask_event_irq()
491 	raw_spin_unlock(&port->lock);  in mc_unmask_event_irq()
549 	return devm_request_irq(plda->dev, event_irq, mc_event_handler,  in mc_request_event_irq()
566 		       port->ctrl_base_addr + SEC_ERROR_INT);  in mc_clear_secs()
567 	writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT);  in mc_clear_secs()
573 		       port->ctrl_base_addr + DED_ERROR_INT);  in mc_clear_deds()
574 	writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT);  in mc_clear_deds()
586 	writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL);  in mc_disable_interrupts()
590 		       port->ctrl_base_addr + SEC_ERROR_INT_MASK);  in mc_disable_interrupts()
595 		       port->ctrl_base_addr + DED_ERROR_INT_MASK);  in mc_disable_interrupts()
599 	writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL);  in mc_disable_interrupts()
600 	writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL);  in mc_disable_interrupts()
601 	writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI);  in mc_disable_interrupts()
610 	writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT);  in mc_disable_interrupts()
613 	writel_relaxed(0, port->bridge_base_addr + IMASK_HOST);  in mc_disable_interrupts()
614 	writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST);  in mc_disable_interrupts()
621 	void __iomem *table_addr = port->bridge_base_addr + table_offset;  in mc_pcie_setup_inbound_atr()
625 	atr_sz = ilog2(size) - 1;  in mc_pcie_setup_inbound_atr()
644 	struct device *dev = &pdev->dev;  in mc_pcie_setup_inbound_ranges()
645 	struct device_node *dn = dev->of_node;  in mc_pcie_setup_inbound_ranges()
651 	 * MPFS PCIe Root Port is 32-bit only, behind a Fabric Interface  in mc_pcie_setup_inbound_ranges()
652 	 * Controller FPGA logic block which contains the AXI-S interface.  in mc_pcie_setup_inbound_ranges()
658 	 * window from 0x0 (CPU space) to specified PCIe space.  in mc_pcie_setup_inbound_ranges()
660 	 * Configuration 2: for use with non-coherent designs; supports two  in mc_pcie_setup_inbound_ranges()
661 	 * 1 GB windows to CPU space; one mapping CPU space 0 to PCIe space  in mc_pcie_setup_inbound_ranges()
662 	 * 0x80000000 and a second mapping CPU space 0x40000000 to PCIe  in mc_pcie_setup_inbound_ranges()
663 	 * space 0xc0000000. This cfg needs two windows because of how the  in mc_pcie_setup_inbound_ranges()
664 	 * MSI space is allocated in the AXI-S range on MPFS.  in mc_pcie_setup_inbound_ranges()
670 	if (device_property_read_bool(dev, "dma-noncoherent")) {  in mc_pcie_setup_inbound_ranges()
682 			/* No DMA range property - setup default */  in mc_pcie_setup_inbound_ranges()
691 				return -EINVAL;  in mc_pcie_setup_inbound_ranges()
702 static int mc_platform_init(struct pci_config_window *cfg)  in mc_platform_init()  argument
704 	struct device *dev = cfg->parent;  in mc_platform_init()
709 	/* Configure address translation table 0 for PCIe config space */  in mc_platform_init()
710 	plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start,  in mc_platform_init()
711 			       cfg->res.start,  in mc_platform_init()
712 			       resource_size(&cfg->res));  in mc_platform_init()
714 	/* Need some fixups in config space */  in mc_platform_init()
715 	mc_pcie_enable_msi(port, cfg->win);  in mc_platform_init()
717 	/* Configure non-config space outbound ranges */  in mc_platform_init()
718 	ret = plda_pcie_setup_iomems(bridge, &port->plda);  in mc_platform_init()
726 	port->plda.event_ops = &mc_event_ops;  in mc_platform_init()
727 	port->plda.event_irq_chip = &mc_event_irq_chip;  in mc_platform_init()
728 	port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0);  in mc_platform_init()
731 	ret = plda_init_interrupts(pdev, &port->plda, &mc_event);  in mc_platform_init()
740 	struct device *dev = &pdev->dev;  in mc_host_probe()
748 		return -ENOMEM;  in mc_host_probe()
750 	plda = &port->plda;  in mc_host_probe()
751 	plda->dev = dev;  in mc_host_probe()
753 	port->bridge_base_addr = devm_platform_ioremap_resource_byname(pdev,  in mc_host_probe()
755 	port->ctrl_base_addr = devm_platform_ioremap_resource_byname(pdev,  in mc_host_probe()
757 	if (!IS_ERR(port->bridge_base_addr) && !IS_ERR(port->ctrl_base_addr))  in mc_host_probe()
769 	port->bridge_base_addr = apb_base_addr + MC_PCIE1_BRIDGE_ADDR;  in mc_host_probe()
770 	port->ctrl_base_addr = apb_base_addr + MC_PCIE1_CTRL_ADDR;  in mc_host_probe()
775 	plda->bridge_addr = port->bridge_base_addr;  in mc_host_probe()
776 	plda->num_events = NUM_EVENTS;  in mc_host_probe()
778 	/* Allow enabling MSI by disabling MSI-X */  in mc_host_probe()
779 	val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0);  in mc_host_probe()
781 	writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0);  in mc_host_probe()
784 	val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0);  in mc_host_probe()
788 	plda->msi.num_vectors = 1 << val;  in mc_host_probe()
791 	plda->msi.vector_phy = readl_relaxed(port->bridge_base_addr + IMSI_ADDR);  in mc_host_probe()
796 		return -ENODEV;  in mc_host_probe()
813 		.compatible = "microchip,pcie-host-1.0",
824 		.name = "microchip-pcie",