Lines Matching +full:msi +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
16 #include <linux/msi.h>
21 #include <linux/pci-ecam.h>
34 /* Egress - Bridge translation registers */
44 /* Ingress - address translations */
52 /* Rxed msg fifo - Interrupt status registers */
111 /* MSI interrupt status mask bits */
147 struct nwl_msi { /* MSI information */
162 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
164 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
170 struct nwl_msi msi; member
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
213 return -ETIMEDOUT; in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device()
232 * nwl_pcie_map_bus - Get configuration base
236 * @where: Offset from base
238 * Return: Base address of the configuration space needed to be
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus()
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
262 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
290 dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
299 dev_err_ratelimited(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
329 generic_handle_domain_irq(pcie->intx_irq_domain, bit); in nwl_pcie_leg_handler()
337 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_handle_msi_irq() local
344 generic_handle_domain_irq(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
376 mask = 1 << data->hwirq; in nwl_mask_intx_irq()
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
390 mask = 1 << data->hwirq; in nwl_unmask_intx_irq()
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
409 irq_set_chip_data(irq, domain->host_data); in nwl_intx_map()
422 .name = "nwl_pcie:msi",
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
441 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
442 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
443 msg->data = data->hwirq; in nwl_compose_msi_msg()
447 .name = "Xilinx MSI",
454 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc()
455 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc() local
459 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
460 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
463 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
464 return -ENOSPC; in nwl_irq_domain_alloc()
469 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
472 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
481 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free() local
483 mutex_lock(&msi->lock); in nwl_irq_domain_free()
484 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
486 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
497 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
498 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
499 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain() local
501 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
503 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
505 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
507 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
509 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
510 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
511 dev_err(dev, "failed to create msi IRQ domain\n"); in nwl_pcie_init_msi_irq_domain()
512 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
513 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
521 int err = phy_power_off(pcie->phy[i]); in nwl_pcie_phy_power_off()
524 dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i, in nwl_pcie_phy_power_off()
530 int err = phy_exit(pcie->phy[i]); in nwl_pcie_phy_exit()
533 dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err); in nwl_pcie_phy_exit()
540 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_phy_enable()
541 ret = phy_init(pcie->phy[i]); in nwl_pcie_phy_enable()
545 ret = phy_power_on(pcie->phy[i]); in nwl_pcie_phy_enable()
555 while (i--) { in nwl_pcie_phy_enable()
567 for (i = ARRAY_SIZE(pcie->phy); i--;) { in nwl_pcie_phy_disable()
575 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
576 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
582 return -EINVAL; in nwl_pcie_init_irq_domain()
585 pcie->intx_irq_domain = irq_domain_add_linear(intc_node, in nwl_pcie_init_irq_domain()
590 if (!pcie->intx_irq_domain) { in nwl_pcie_init_irq_domain()
592 return -ENOMEM; in nwl_pcie_init_irq_domain()
595 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
602 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
604 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi() local
605 unsigned long base; in nwl_pcie_enable_msi() local
608 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
611 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
612 if (msi->irq_msi1 < 0) in nwl_pcie_enable_msi()
613 return -EINVAL; in nwl_pcie_enable_msi()
615 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
619 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
620 if (msi->irq_msi0 < 0) in nwl_pcie_enable_msi()
621 return -EINVAL; in nwl_pcie_enable_msi()
623 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
629 dev_err(dev, "MSI not present\n"); in nwl_pcie_enable_msi()
630 return -EIO; in nwl_pcie_enable_msi()
642 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
643 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
644 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
647 * For high range MSI interrupts: disable, clear any pending, in nwl_pcie_enable_msi()
658 * For low range MSI interrupts: disable, clear any pending, in nwl_pcie_enable_msi()
673 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
684 /* Write bridge_off to breg base */ in nwl_pcie_bridge_init()
685 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
687 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
706 if (of_dma_is_coherent(dev->of_node)) in nwl_pcie_bridge_init()
728 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
730 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
739 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
740 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
741 return -EINVAL; in nwl_pcie_bridge_init()
743 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
748 pcie->irq_misc); in nwl_pcie_bridge_init()
782 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
787 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
788 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
789 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
790 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
793 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
794 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
795 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
796 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
799 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
800 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
801 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
802 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
805 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
806 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
807 return pcie->irq_intx; in nwl_pcie_parse_dt()
809 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
813 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_parse_dt()
814 pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); in nwl_pcie_parse_dt()
815 if (PTR_ERR(pcie->phy[i]) == -ENODEV) { in nwl_pcie_parse_dt()
816 pcie->phy[i] = NULL; in nwl_pcie_parse_dt()
820 if (IS_ERR(pcie->phy[i])) in nwl_pcie_parse_dt()
821 return PTR_ERR(pcie->phy[i]); in nwl_pcie_parse_dt()
828 { .compatible = "xlnx,nwl-pcie-2.11", },
834 struct device *dev = &pdev->dev; in nwl_pcie_probe()
841 return -ENODEV; in nwl_pcie_probe()
846 pcie->dev = dev; in nwl_pcie_probe()
854 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
855 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
856 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
858 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
882 bridge->sysdata = pcie; in nwl_pcie_probe()
883 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
888 dev_err(dev, "failed to enable MSI support: %d\n", err); in nwl_pcie_probe()
900 clk_disable_unprepare(pcie->clk); in nwl_pcie_probe()
909 clk_disable_unprepare(pcie->clk); in nwl_pcie_remove()
914 .name = "nwl-pcie",