1 // SPDX-License-Identifier: GPL-2.0+
7  * Author: Shawn Lin <shawn.lin@rock-chips.com>
8  *         Wenrui Li <wenrui.li@rock-chips.com>
22 #include <linux/reset.h>
25 #include "pcie-rockchip.h"
29 	struct device *dev = rockchip->dev;  in rockchip_pcie_parse_dt()
31 	struct device_node *node = dev->of_node;  in rockchip_pcie_parse_dt()
35 	if (rockchip->is_rc) {  in rockchip_pcie_parse_dt()
38 						    "axi-base");  in rockchip_pcie_parse_dt()
39 		rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);  in rockchip_pcie_parse_dt()
40 		if (IS_ERR(rockchip->reg_base))  in rockchip_pcie_parse_dt()
41 			return PTR_ERR(rockchip->reg_base);  in rockchip_pcie_parse_dt()
43 		rockchip->mem_res =  in rockchip_pcie_parse_dt()
45 						     "mem-base");  in rockchip_pcie_parse_dt()
46 		if (!rockchip->mem_res)  in rockchip_pcie_parse_dt()
47 			return -EINVAL;  in rockchip_pcie_parse_dt()
50 	rockchip->apb_base =  in rockchip_pcie_parse_dt()
51 		devm_platform_ioremap_resource_byname(pdev, "apb-base");  in rockchip_pcie_parse_dt()
52 	if (IS_ERR(rockchip->apb_base))  in rockchip_pcie_parse_dt()
53 		return PTR_ERR(rockchip->apb_base);  in rockchip_pcie_parse_dt()
59 	rockchip->lanes = 1;  in rockchip_pcie_parse_dt()
60 	err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);  in rockchip_pcie_parse_dt()
61 	if (!err && (rockchip->lanes == 0 ||  in rockchip_pcie_parse_dt()
62 		     rockchip->lanes == 3 ||  in rockchip_pcie_parse_dt()
63 		     rockchip->lanes > 4)) {  in rockchip_pcie_parse_dt()
64 		dev_warn(dev, "invalid num-lanes, default to use one lane\n");  in rockchip_pcie_parse_dt()
65 		rockchip->lanes = 1;  in rockchip_pcie_parse_dt()
68 	rockchip->link_gen = of_pci_get_max_link_speed(node);  in rockchip_pcie_parse_dt()
69 	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)  in rockchip_pcie_parse_dt()
70 		rockchip->link_gen = 2;  in rockchip_pcie_parse_dt()
73 		rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i];  in rockchip_pcie_parse_dt()
77 						    rockchip->pm_rsts);  in rockchip_pcie_parse_dt()
79 		return dev_err_probe(dev, err, "Cannot get the PM reset\n");  in rockchip_pcie_parse_dt()
82 		rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i];  in rockchip_pcie_parse_dt()
86 						    rockchip->core_rsts);  in rockchip_pcie_parse_dt()
90 	if (rockchip->is_rc)  in rockchip_pcie_parse_dt()
91 		rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep",  in rockchip_pcie_parse_dt()
94 		rockchip->perst_gpio = devm_gpiod_get_optional(dev, "reset",  in rockchip_pcie_parse_dt()
96 	if (IS_ERR(rockchip->perst_gpio))  in rockchip_pcie_parse_dt()
97 		return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio),  in rockchip_pcie_parse_dt()
100 	rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);  in rockchip_pcie_parse_dt()
101 	if (rockchip->num_clks < 0)  in rockchip_pcie_parse_dt()
102 		return dev_err_probe(dev, rockchip->num_clks,  in rockchip_pcie_parse_dt()
110 /* 100 ms max wait time for PHY PLLs to lock */
112 /* Sleep should be less than 20ms */
117 	struct device *dev = rockchip->dev;  in rockchip_pcie_init_port()
122 					rockchip->pm_rsts);  in rockchip_pcie_init_port()
124 		return dev_err_probe(dev, err, "Couldn't assert PM resets\n");  in rockchip_pcie_init_port()
127 		err = phy_init(rockchip->phys[i]);  in rockchip_pcie_init_port()
135 					rockchip->core_rsts);  in rockchip_pcie_init_port()
137 		dev_err_probe(dev, err, "Couldn't assert Core resets\n");  in rockchip_pcie_init_port()
144 					  rockchip->pm_rsts);  in rockchip_pcie_init_port()
150 	if (rockchip->link_gen == 2)  in rockchip_pcie_init_port()
158 	       PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);  in rockchip_pcie_init_port()
160 	if (rockchip->is_rc)  in rockchip_pcie_init_port()
169 		err = phy_power_on(rockchip->phys[i]);  in rockchip_pcie_init_port()
187 					  rockchip->core_rsts);  in rockchip_pcie_init_port()
189 		dev_err(dev, "Couldn't deassert Core reset %d\n", err);  in rockchip_pcie_init_port()
195 	while (i--)  in rockchip_pcie_init_port()
196 		phy_power_off(rockchip->phys[i]);  in rockchip_pcie_init_port()
199 	while (i--)  in rockchip_pcie_init_port()
200 		phy_exit(rockchip->phys[i]);  in rockchip_pcie_init_port()
207 	struct device *dev = rockchip->dev;  in rockchip_pcie_get_phys()
212 	phy = devm_phy_get(dev, "pcie-phy");  in rockchip_pcie_get_phys()
214 		rockchip->legacy_phy = true;  in rockchip_pcie_get_phys()
215 		rockchip->phys[0] = phy;  in rockchip_pcie_get_phys()
220 	if (PTR_ERR(phy) == -EPROBE_DEFER)  in rockchip_pcie_get_phys()
223 	dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");  in rockchip_pcie_get_phys()
226 		name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);  in rockchip_pcie_get_phys()
228 			return -ENOMEM;  in rockchip_pcie_get_phys()
230 		phy = devm_of_phy_get(dev, dev->of_node, name);  in rockchip_pcie_get_phys()
234 			if (PTR_ERR(phy) != -EPROBE_DEFER)  in rockchip_pcie_get_phys()
240 		rockchip->phys[i] = phy;  in rockchip_pcie_get_phys()
253 		if (rockchip->lanes_map & BIT(i))  in rockchip_pcie_deinit_phys()
254 			phy_power_off(rockchip->phys[i]);  in rockchip_pcie_deinit_phys()
255 		phy_exit(rockchip->phys[i]);  in rockchip_pcie_deinit_phys()
262 	struct device *dev = rockchip->dev;  in rockchip_pcie_enable_clocks()
265 	err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks);  in rockchip_pcie_enable_clocks()
276 	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);  in rockchip_pcie_disable_clocks()