Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
37 #define MSI_ENABLE_CFG_SHIFT 0
40 #define CFG_IND_ADDR_MASK 0x00001ffc
42 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
45 #define SYS_RC_INTX_MASK 0xf
52 #define APB_ERR_EN_SHIFT 0
55 #define CFG_RD_SUCCESS 0
59 #define CFG_RETRY_STATUS 0xffff0001
71 #define OARR_VALID_SHIFT 0
81 #define IMAP_VALID_SHIFT 0
84 #define IPROC_PCI_PM_CAP 0x48
85 #define IPROC_PCI_PM_CAP_MASK 0xffff
86 #define IPROC_PCI_EXP_CAP 0xac
88 #define IPROC_PCIE_REG_INVALID 0xffff
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
144 IPROC_PCIE_IB_MAP_MEM = 0,
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
181 .imap_addr_offset = 0x40,
182 .imap_window_offset = 0x4,
191 .imap_addr_offset = 0x4,
192 .imap_window_offset = 0x8,
203 .imap_addr_offset = 0x4,
204 .imap_window_offset = 0x8,
213 .imap_addr_offset = 0x4,
214 .imap_window_offset = 0x8,
223 .imap_addr_offset = 0x4,
224 .imap_window_offset = 0x8,
229 * iProc PCIe host registers
233 IPROC_PCIE_CLK_CTRL = 0,
306 /* iProc PCIe PAXB BCMA registers */
308 [IPROC_PCIE_CLK_CTRL] = 0x000,
309 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
310 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
311 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
312 [IPROC_PCIE_CFG_DATA] = 0x1fc,
313 [IPROC_PCIE_INTX_EN] = 0x330,
314 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
317 /* iProc PCIe PAXB registers */
319 [IPROC_PCIE_CLK_CTRL] = 0x000,
320 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
321 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
322 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
323 [IPROC_PCIE_CFG_DATA] = 0x1fc,
324 [IPROC_PCIE_INTX_EN] = 0x330,
325 [IPROC_PCIE_OARR0] = 0xd20,
326 [IPROC_PCIE_OMAP0] = 0xd40,
327 [IPROC_PCIE_OARR1] = 0xd28,
328 [IPROC_PCIE_OMAP1] = 0xd48,
329 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
330 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
333 /* iProc PCIe PAXB v2 registers */
335 [IPROC_PCIE_CLK_CTRL] = 0x000,
336 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
337 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
338 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
339 [IPROC_PCIE_CFG_DATA] = 0x1fc,
340 [IPROC_PCIE_INTX_EN] = 0x330,
341 [IPROC_PCIE_OARR0] = 0xd20,
342 [IPROC_PCIE_OMAP0] = 0xd40,
343 [IPROC_PCIE_OARR1] = 0xd28,
344 [IPROC_PCIE_OMAP1] = 0xd48,
345 [IPROC_PCIE_OARR2] = 0xd60,
346 [IPROC_PCIE_OMAP2] = 0xd68,
347 [IPROC_PCIE_OARR3] = 0xdf0,
348 [IPROC_PCIE_OMAP3] = 0xdf8,
349 [IPROC_PCIE_IARR0] = 0xd00,
350 [IPROC_PCIE_IMAP0] = 0xc00,
351 [IPROC_PCIE_IARR1] = 0xd08,
352 [IPROC_PCIE_IMAP1] = 0xd70,
353 [IPROC_PCIE_IARR2] = 0xd10,
354 [IPROC_PCIE_IMAP2] = 0xcc0,
355 [IPROC_PCIE_IARR3] = 0xe00,
356 [IPROC_PCIE_IMAP3] = 0xe08,
357 [IPROC_PCIE_IARR4] = 0xe68,
358 [IPROC_PCIE_IMAP4] = 0xe70,
359 [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
360 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
361 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
364 /* iProc PCIe PAXC v1 registers */
366 [IPROC_PCIE_CLK_CTRL] = 0x000,
367 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
368 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
369 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
370 [IPROC_PCIE_CFG_DATA] = 0x1fc,
373 /* iProc PCIe PAXC v2 registers */
375 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
376 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
377 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
378 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
379 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
380 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
381 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
382 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
383 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
384 [IPROC_PCIE_CFG_DATA] = 0x1fc,
392 0x16cd,
393 0x16f0,
394 0xd802,
395 0xd804
400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data() local
401 return pcie; in iproc_data()
409 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, in iproc_pcie_reg_offset() argument
412 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
415 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, in iproc_pcie_read_reg() argument
418 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_read_reg()
421 return 0; in iproc_pcie_read_reg()
423 return readl(pcie->base + offset); in iproc_pcie_read_reg()
426 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, in iproc_pcie_write_reg() argument
429 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_write_reg()
434 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
440 * (typically seen during enumeration with multi-function devices) from
446 struct iproc_pcie *pcie = iproc_data(bus); in iproc_pcie_apb_err_disable() local
449 if (bus->number && pcie->has_apb_err_disable) { in iproc_pcie_apb_err_disable()
450 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); in iproc_pcie_apb_err_disable()
455 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); in iproc_pcie_apb_err_disable()
459 static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, in iproc_pcie_map_ep_cfg_reg() argument
471 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); in iproc_pcie_map_ep_cfg_reg()
472 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); in iproc_pcie_map_ep_cfg_reg()
477 return (pcie->base + offset); in iproc_pcie_map_ep_cfg_reg()
480 static unsigned int iproc_pcie_cfg_retry(struct iproc_pcie *pcie, in iproc_pcie_cfg_retry() argument
488 * As per PCIe r6.0, sec 2.3.2, Config RRS Software Visibility only in iproc_pcie_cfg_retry()
499 * Note that a non-Vendor ID config register may have a value of in iproc_pcie_cfg_retry()
502 * eventually return the wrong data (0xffffffff). in iproc_pcie_cfg_retry()
505 while (data == CFG_RETRY_STATUS && timeout--) { in iproc_pcie_cfg_retry()
511 status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS); in iproc_pcie_cfg_retry()
520 data = 0xffffffff; in iproc_pcie_cfg_retry()
525 static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, u32 *val) in iproc_pcie_fix_cap() argument
529 switch (where & ~0x3) { in iproc_pcie_fix_cap()
537 for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++) in iproc_pcie_fix_cap()
539 pcie->fix_paxc_cap = true; in iproc_pcie_fix_cap()
543 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
544 /* advertise PM, force next capability to PCIe */ in iproc_pcie_fix_cap()
551 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
571 struct iproc_pcie *pcie = iproc_data(bus); in iproc_pcie_config_read() local
572 unsigned int busno = bus->number; in iproc_pcie_config_read()
578 if (busno == 0) { in iproc_pcie_config_read()
581 iproc_pcie_fix_cap(pcie, where, val); in iproc_pcie_config_read()
586 cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); in iproc_pcie_config_read()
591 data = iproc_pcie_cfg_retry(pcie, cfg_data_p); in iproc_pcie_config_read()
595 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pcie_config_read()
605 * ID of 0x168e (PCI_DEVICE_ID_NX2_57810), we try to catch those access in iproc_pcie_config_read()
608 #define DEVICE_ID_MASK 0xffff0000 in iproc_pcie_config_read()
610 if (pcie->rej_unconfig_pf && in iproc_pcie_config_read()
623 static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, in iproc_pcie_map_cfg_bus() argument
630 if (busno == 0) { in iproc_pcie_map_cfg_bus()
631 if (PCIE_ECAM_DEVFN(devfn) > 0) in iproc_pcie_map_cfg_bus()
634 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, in iproc_pcie_map_cfg_bus()
636 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); in iproc_pcie_map_cfg_bus()
640 return (pcie->base + offset); in iproc_pcie_map_cfg_bus()
643 return iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); in iproc_pcie_map_cfg_bus()
650 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, in iproc_pcie_bus_map_cfg_bus()
654 static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, in iproc_pci_raw_config_read32() argument
660 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); in iproc_pci_raw_config_read32()
667 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pci_raw_config_read32()
672 static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, in iproc_pci_raw_config_write32() argument
679 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); in iproc_pci_raw_config_write32()
688 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); in iproc_pci_raw_config_write32()
690 tmp |= val << ((where & 0x3) * 8); in iproc_pci_raw_config_write32()
700 struct iproc_pcie *pcie = iproc_data(bus); in iproc_pcie_config_read32() local
703 if (pcie->iproc_cfg_read) in iproc_pcie_config_read32()
730 static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert) in iproc_pcie_perst_ctrl() argument
739 if (pcie->ep_is_internal) in iproc_pcie_perst_ctrl()
743 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); in iproc_pcie_perst_ctrl()
746 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); in iproc_pcie_perst_ctrl()
749 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); in iproc_pcie_perst_ctrl()
751 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); in iproc_pcie_perst_ctrl()
756 int iproc_pcie_shutdown(struct iproc_pcie *pcie) in iproc_pcie_shutdown() argument
758 iproc_pcie_perst_ctrl(pcie, true); in iproc_pcie_shutdown()
761 return 0; in iproc_pcie_shutdown()
765 static int iproc_pcie_check_link(struct iproc_pcie *pcie) in iproc_pcie_check_link() argument
767 struct device *dev = pcie->dev; in iproc_pcie_check_link()
775 if (pcie->ep_is_internal) in iproc_pcie_check_link()
776 return 0; in iproc_pcie_check_link()
778 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); in iproc_pcie_check_link()
781 return -ENODEV; in iproc_pcie_check_link()
785 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); in iproc_pcie_check_link()
788 return -EFAULT; in iproc_pcie_check_link()
791 /* force class to PCI_CLASS_BRIDGE_PCI_NORMAL (0x060400) */ in iproc_pcie_check_link()
792 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c in iproc_pcie_check_link()
793 #define PCI_BRIDGE_CTRL_REG_CLASS_MASK 0xffffff in iproc_pcie_check_link()
794 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, in iproc_pcie_check_link()
798 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, in iproc_pcie_check_link()
802 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, in iproc_pcie_check_link()
809 #define PCI_TARGET_LINK_SPEED_MASK 0xf in iproc_pcie_check_link()
810 #define PCI_TARGET_LINK_SPEED_GEN2 0x2 in iproc_pcie_check_link()
811 #define PCI_TARGET_LINK_SPEED_GEN1 0x1 in iproc_pcie_check_link()
812 iproc_pci_raw_config_read32(pcie, 0, in iproc_pcie_check_link()
819 iproc_pci_raw_config_write32(pcie, 0, in iproc_pcie_check_link()
824 iproc_pci_raw_config_read32(pcie, 0, in iproc_pcie_check_link()
834 return link_is_active ? 0 : -ENODEV; in iproc_pcie_check_link()
837 static void iproc_pcie_enable(struct iproc_pcie *pcie) in iproc_pcie_enable() argument
839 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); in iproc_pcie_enable()
842 static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, in iproc_pcie_ob_is_valid() argument
847 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); in iproc_pcie_ob_is_valid()
852 static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx, in iproc_pcie_ob_write() argument
855 struct device *dev = pcie->dev; in iproc_pcie_ob_write()
862 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0, in iproc_pcie_ob_write()
864 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0, in iproc_pcie_ob_write()
868 return -EINVAL; in iproc_pcie_ob_write()
871 * Program the OARR registers. The upper 32-bit OARR register is in iproc_pcie_ob_write()
872 * always right after the lower 32-bit OARR register. in iproc_pcie_ob_write()
875 OARR_VALID, pcie->base + oarr_offset); in iproc_pcie_ob_write()
876 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); in iproc_pcie_ob_write()
879 writel(lower_32_bits(pci_addr), pcie->base + omap_offset); in iproc_pcie_ob_write()
880 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); in iproc_pcie_ob_write()
882 dev_dbg(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", in iproc_pcie_ob_write()
884 dev_dbg(dev, "oarr lo 0x%x oarr hi 0x%x\n", in iproc_pcie_ob_write()
885 readl(pcie->base + oarr_offset), in iproc_pcie_ob_write()
886 readl(pcie->base + oarr_offset + 4)); in iproc_pcie_ob_write()
887 dev_dbg(dev, "omap lo 0x%x omap hi 0x%x\n", in iproc_pcie_ob_write()
888 readl(pcie->base + omap_offset), in iproc_pcie_ob_write()
889 readl(pcie->base + omap_offset + 4)); in iproc_pcie_ob_write()
891 return 0; in iproc_pcie_ob_write()
899 * iproc_pcie_address = axi_address - axi_offset
903 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
905 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, in iproc_pcie_setup_ob() argument
908 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_setup_ob()
909 struct device *dev = pcie->dev; in iproc_pcie_setup_ob()
910 int ret = -EINVAL, window_idx, size_idx; in iproc_pcie_setup_ob()
912 if (axi_addr < ob->axi_offset) { in iproc_pcie_setup_ob()
914 &axi_addr, &ob->axi_offset); in iproc_pcie_setup_ob()
915 return -EINVAL; in iproc_pcie_setup_ob()
920 * PCIe core before programming the OARR in iproc_pcie_setup_ob()
922 axi_addr -= ob->axi_offset; in iproc_pcie_setup_ob()
925 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { in iproc_pcie_setup_ob()
927 &pcie->ob_map[window_idx]; in iproc_pcie_setup_ob()
933 if (iproc_pcie_ob_is_valid(pcie, window_idx)) in iproc_pcie_setup_ob()
941 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; in iproc_pcie_setup_ob()
942 size_idx--) { in iproc_pcie_setup_ob()
944 ob_map->window_sizes[size_idx] * SZ_1M; in iproc_pcie_setup_ob()
953 if (size_idx > 0 || window_idx > 0) in iproc_pcie_setup_ob()
971 return -EINVAL; in iproc_pcie_setup_ob()
978 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx, in iproc_pcie_setup_ob()
983 size -= window_size; in iproc_pcie_setup_ob()
984 if (size == 0) in iproc_pcie_setup_ob()
985 return 0; in iproc_pcie_setup_ob()
1002 &axi_addr, &ob->axi_offset, &pci_addr, &size); in iproc_pcie_setup_ob()
1007 static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, in iproc_pcie_map_ranges() argument
1010 struct device *dev = pcie->dev; in iproc_pcie_map_ranges()
1015 struct resource *res = window->res; in iproc_pcie_map_ranges()
1023 ret = iproc_pcie_setup_ob(pcie, res->start, in iproc_pcie_map_ranges()
1024 res->start - window->offset, in iproc_pcie_map_ranges()
1031 return -EINVAL; in iproc_pcie_map_ranges()
1035 return 0; in iproc_pcie_map_ranges()
1038 static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie, in iproc_pcie_ib_is_in_use() argument
1041 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_is_in_use()
1044 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); in iproc_pcie_ib_is_in_use()
1046 return !!(val & (BIT(ib_map->nr_sizes) - 1)); in iproc_pcie_ib_is_in_use()
1052 return !!(ib_map->type == type); in iproc_pcie_ib_check_type()
1055 static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx, in iproc_pcie_ib_write() argument
1059 struct device *dev = pcie->dev; in iproc_pcie_ib_write()
1060 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_write()
1065 iarr_offset = iproc_pcie_reg_offset(pcie, in iproc_pcie_ib_write()
1067 imap_offset = iproc_pcie_reg_offset(pcie, in iproc_pcie_ib_write()
1071 return -EINVAL; in iproc_pcie_ib_write()
1073 dev_dbg(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", in iproc_pcie_ib_write()
1077 * Program the IARR registers. The upper 32-bit IARR register is in iproc_pcie_ib_write()
1078 * always right after the lower 32-bit IARR register. in iproc_pcie_ib_write()
1081 pcie->base + iarr_offset); in iproc_pcie_ib_write()
1082 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); in iproc_pcie_ib_write()
1084 dev_dbg(dev, "iarr lo 0x%x iarr hi 0x%x\n", in iproc_pcie_ib_write()
1085 readl(pcie->base + iarr_offset), in iproc_pcie_ib_write()
1086 readl(pcie->base + iarr_offset + 4)); in iproc_pcie_ib_write()
1093 for (window_idx = 0; window_idx < nr_windows; window_idx++) { in iproc_pcie_ib_write()
1094 val = readl(pcie->base + imap_offset); in iproc_pcie_ib_write()
1096 writel(val, pcie->base + imap_offset); in iproc_pcie_ib_write()
1098 pcie->base + imap_offset + ib_map->imap_addr_offset); in iproc_pcie_ib_write()
1100 dev_dbg(dev, "imap window [%d] lo 0x%x hi 0x%x\n", in iproc_pcie_ib_write()
1101 window_idx, readl(pcie->base + imap_offset), in iproc_pcie_ib_write()
1102 readl(pcie->base + imap_offset + in iproc_pcie_ib_write()
1103 ib_map->imap_addr_offset)); in iproc_pcie_ib_write()
1105 imap_offset += ib_map->imap_window_offset; in iproc_pcie_ib_write()
1109 return 0; in iproc_pcie_ib_write()
1112 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, in iproc_pcie_setup_ib() argument
1116 struct device *dev = pcie->dev; in iproc_pcie_setup_ib()
1117 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_setup_ib()
1120 u64 axi_addr = entry->res->start; in iproc_pcie_setup_ib()
1121 u64 pci_addr = entry->res->start - entry->offset; in iproc_pcie_setup_ib()
1122 resource_size_t size = resource_size(entry->res); in iproc_pcie_setup_ib()
1125 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { in iproc_pcie_setup_ib()
1127 &pcie->ib_map[region_idx]; in iproc_pcie_setup_ib()
1133 if (iproc_pcie_ib_is_in_use(pcie, region_idx) || in iproc_pcie_setup_ib()
1138 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { in iproc_pcie_setup_ib()
1140 ib_map->region_sizes[size_idx] * ib_map->size_unit; in iproc_pcie_setup_ib()
1150 return -EINVAL; in iproc_pcie_setup_ib()
1154 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx, in iproc_pcie_setup_ib()
1155 ib_map->nr_windows, axi_addr, in iproc_pcie_setup_ib()
1160 return 0; in iproc_pcie_setup_ib()
1164 ret = -EINVAL; in iproc_pcie_setup_ib()
1174 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) in iproc_pcie_map_dma_ranges() argument
1176 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in iproc_pcie_map_dma_ranges()
1178 int ret = 0; in iproc_pcie_map_dma_ranges()
1180 resource_list_for_each_entry(entry, &host->dma_ranges) { in iproc_pcie_map_dma_ranges()
1182 ret = iproc_pcie_setup_ib(pcie, entry, IPROC_PCIE_IB_MAP_MEM); in iproc_pcie_map_dma_ranges()
1190 static void iproc_pcie_invalidate_mapping(struct iproc_pcie *pcie) in iproc_pcie_invalidate_mapping() argument
1192 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_invalidate_mapping()
1193 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_invalidate_mapping()
1196 if (pcie->ep_is_internal) in iproc_pcie_invalidate_mapping()
1199 if (pcie->need_ob_cfg) { in iproc_pcie_invalidate_mapping()
1201 for (idx = ob->nr_windows - 1; idx >= 0; idx--) { in iproc_pcie_invalidate_mapping()
1202 iproc_pcie_write_reg(pcie, in iproc_pcie_invalidate_mapping()
1203 MAP_REG(IPROC_PCIE_OARR0, idx), 0); in iproc_pcie_invalidate_mapping()
1207 if (pcie->need_ib_cfg) { in iproc_pcie_invalidate_mapping()
1209 for (idx = 0; idx < ib->nr_regions; idx++) { in iproc_pcie_invalidate_mapping()
1210 iproc_pcie_write_reg(pcie, in iproc_pcie_invalidate_mapping()
1211 MAP_REG(IPROC_PCIE_IARR0, idx), 0); in iproc_pcie_invalidate_mapping()
1216 static int iproce_pcie_get_msi(struct iproc_pcie *pcie, in iproce_pcie_get_msi() argument
1220 struct device *dev = pcie->dev; in iproce_pcie_get_msi()
1225 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only in iproce_pcie_get_msi()
1228 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { in iproce_pcie_get_msi()
1230 return -ENODEV; in iproce_pcie_get_msi()
1234 ret = of_address_to_resource(msi_node, 0, &res); in iproce_pcie_get_msi()
1235 if (ret < 0) { in iproce_pcie_get_msi()
1241 return 0; in iproce_pcie_get_msi()
1244 static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) in iproc_pcie_paxb_v2_msi_steer() argument
1249 memset(&entry, 0, sizeof(entry)); in iproc_pcie_paxb_v2_msi_steer()
1252 msi_addr &= ~(SZ_32K - 1); in iproc_pcie_paxb_v2_msi_steer()
1253 entry.res->start = msi_addr; in iproc_pcie_paxb_v2_msi_steer()
1254 entry.res->end = msi_addr + SZ_32K - 1; in iproc_pcie_paxb_v2_msi_steer()
1256 ret = iproc_pcie_setup_ib(pcie, &entry, IPROC_PCIE_IB_MAP_IO); in iproc_pcie_paxb_v2_msi_steer()
1260 static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr, in iproc_pcie_paxc_v2_msi_steer() argument
1268 * treated as non-MSI transfers in iproc_pcie_paxc_v2_msi_steer()
1270 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); in iproc_pcie_paxc_v2_msi_steer()
1272 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); in iproc_pcie_paxc_v2_msi_steer()
1278 * bits [30:0] of the MSI base address register. In fact, in all iProc in iproc_pcie_paxc_v2_msi_steer()
1279 * based SoCs, all I/O register bases are well below the 32-bit in iproc_pcie_paxc_v2_msi_steer()
1282 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR, in iproc_pcie_paxc_v2_msi_steer()
1286 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); in iproc_pcie_paxc_v2_msi_steer()
1289 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); in iproc_pcie_paxc_v2_msi_steer()
1291 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); in iproc_pcie_paxc_v2_msi_steer()
1298 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI, in iproc_pcie_paxc_v2_msi_steer()
1300 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO, in iproc_pcie_paxc_v2_msi_steer()
1304 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); in iproc_pcie_paxc_v2_msi_steer()
1306 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); in iproc_pcie_paxc_v2_msi_steer()
1309 static int iproc_pcie_msi_steer(struct iproc_pcie *pcie, in iproc_pcie_msi_steer() argument
1312 struct device *dev = pcie->dev; in iproc_pcie_msi_steer()
1316 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr); in iproc_pcie_msi_steer()
1317 if (ret < 0) { in iproc_pcie_msi_steer()
1322 switch (pcie->type) { in iproc_pcie_msi_steer()
1324 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr); in iproc_pcie_msi_steer()
1329 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr, true); in iproc_pcie_msi_steer()
1332 return -EINVAL; in iproc_pcie_msi_steer()
1335 return 0; in iproc_pcie_msi_steer()
1338 static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) in iproc_pcie_msi_enable() argument
1344 * Either the "msi-parent" or the "msi-map" phandle needs to exist in iproc_pcie_msi_enable()
1348 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); in iproc_pcie_msi_enable()
1354 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); in iproc_pcie_msi_enable()
1356 return -ENODEV; in iproc_pcie_msi_enable()
1361 return -ENODEV; in iproc_pcie_msi_enable()
1365 * Certain revisions of the iProc PCIe controller require additional in iproc_pcie_msi_enable()
1369 if (pcie->need_msi_steer) { in iproc_pcie_msi_enable()
1370 ret = iproc_pcie_msi_steer(pcie, msi_node); in iproc_pcie_msi_enable()
1379 ret = iproc_msi_init(pcie, msi_node); in iproc_pcie_msi_enable()
1386 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) in iproc_pcie_msi_disable() argument
1388 iproc_msi_exit(pcie); in iproc_pcie_msi_disable()
1391 static int iproc_pcie_rev_init(struct iproc_pcie *pcie) in iproc_pcie_rev_init() argument
1393 struct device *dev = pcie->dev; in iproc_pcie_rev_init()
1397 switch (pcie->type) { in iproc_pcie_rev_init()
1403 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1404 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1405 pcie->ob_map = paxb_ob_map; in iproc_pcie_rev_init()
1406 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); in iproc_pcie_rev_init()
1411 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1412 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1413 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1414 pcie->ob_map = paxb_v2_ob_map; in iproc_pcie_rev_init()
1415 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); in iproc_pcie_rev_init()
1417 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); in iproc_pcie_rev_init()
1418 pcie->ib_map = paxb_v2_ib_map; in iproc_pcie_rev_init()
1419 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1425 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1426 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1427 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1431 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1432 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1433 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1434 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1437 dev_err(dev, "incompatible iProc PCIe interface\n"); in iproc_pcie_rev_init()
1438 return -EINVAL; in iproc_pcie_rev_init()
1441 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, in iproc_pcie_rev_init()
1442 sizeof(*pcie->reg_offsets), in iproc_pcie_rev_init()
1444 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
1445 return -ENOMEM; in iproc_pcie_rev_init()
1448 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1449 IPROC_PCIE_REG_INVALID : regs[0]; in iproc_pcie_rev_init()
1451 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
1454 return 0; in iproc_pcie_rev_init()
1457 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) in iproc_pcie_setup() argument
1462 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in iproc_pcie_setup()
1464 dev = pcie->dev; in iproc_pcie_setup()
1466 ret = iproc_pcie_rev_init(pcie); in iproc_pcie_setup()
1472 ret = phy_init(pcie->phy); in iproc_pcie_setup()
1474 dev_err(dev, "unable to initialize PCIe PHY\n"); in iproc_pcie_setup()
1478 ret = phy_power_on(pcie->phy); in iproc_pcie_setup()
1480 dev_err(dev, "unable to power on PCIe PHY\n"); in iproc_pcie_setup()
1484 iproc_pcie_perst_ctrl(pcie, true); in iproc_pcie_setup()
1485 iproc_pcie_perst_ctrl(pcie, false); in iproc_pcie_setup()
1487 iproc_pcie_invalidate_mapping(pcie); in iproc_pcie_setup()
1489 if (pcie->need_ob_cfg) { in iproc_pcie_setup()
1490 ret = iproc_pcie_map_ranges(pcie, res); in iproc_pcie_setup()
1497 if (pcie->need_ib_cfg) { in iproc_pcie_setup()
1498 ret = iproc_pcie_map_dma_ranges(pcie); in iproc_pcie_setup()
1499 if (ret && ret != -ENOENT) in iproc_pcie_setup()
1503 ret = iproc_pcie_check_link(pcie); in iproc_pcie_setup()
1505 dev_err(dev, "no PCIe EP device detected\n"); in iproc_pcie_setup()
1509 iproc_pcie_enable(pcie); in iproc_pcie_setup()
1512 if (iproc_pcie_msi_enable(pcie)) in iproc_pcie_setup()
1515 host->ops = &iproc_pcie_ops; in iproc_pcie_setup()
1516 host->sysdata = pcie; in iproc_pcie_setup()
1517 host->map_irq = pcie->map_irq; in iproc_pcie_setup()
1520 if (ret < 0) { in iproc_pcie_setup()
1525 for_each_pci_bridge(pdev, host->bus) { in iproc_pcie_setup()
1530 return 0; in iproc_pcie_setup()
1533 phy_power_off(pcie->phy); in iproc_pcie_setup()
1535 phy_exit(pcie->phy); in iproc_pcie_setup()
1540 void iproc_pcie_remove(struct iproc_pcie *pcie) in iproc_pcie_remove() argument
1542 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in iproc_pcie_remove()
1544 pci_stop_root_bus(host->bus); in iproc_pcie_remove()
1545 pci_remove_root_bus(host->bus); in iproc_pcie_remove()
1547 iproc_pcie_msi_disable(pcie); in iproc_pcie_remove()
1549 phy_power_off(pcie->phy); in iproc_pcie_remove()
1550 phy_exit(pcie->phy); in iproc_pcie_remove()
1560 struct iproc_pcie *pcie = iproc_data(pdev->bus); in quirk_paxc_disable_msi_parsing() local
1562 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_disable_msi_parsing()
1563 iproc_pcie_paxc_v2_msi_steer(pcie, 0, false); in quirk_paxc_disable_msi_parsing()
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0,
1567 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802,
1569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,
1579 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_bridge()
1580 pdev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in quirk_paxc_bridge()
1583 * MPSS is not being set properly (as it is currently 0). This is in quirk_paxc_bridge()
1588 pdev->pcie_mpss = 2; in quirk_paxc_bridge()
1590 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
1591 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
1592 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
1593 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
1594 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
1597 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");