Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
38 #define BRCM_PCIE_CAP_REGS 0x00ac
40 /* Broadcom STB PCIe Register Offsets */
41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
43 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
45 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
46 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
48 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
51 #define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
52 #define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
54 #define PCIE_RC_DL_MDIO_ADDR 0x1100
55 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
56 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
58 #define PCIE_MISC_MISC_CTRL 0x4008
59 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
60 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
61 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
62 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
63 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
65 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
66 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
67 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
70 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
74 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
86 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
87 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
89 #define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
92 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
93 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
95 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
96 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
97 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
99 #define PCIE_MISC_PCIE_CTRL 0x4064
100 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
101 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
103 #define PCIE_MISC_PCIE_STATUS 0x4068
104 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
105 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
106 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
107 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
109 #define PCIE_MISC_REVISION 0x406c
110 #define BRCM_PCIE_HW_REV_33 0x0303
111 #define BRCM_PCIE_HW_REV_3_20 0x0320
113 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
114 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
115 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
119 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
120 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
124 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
125 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
129 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
130 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
131 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
132 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
137 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
138 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0)
139 #define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c
141 #define PCIE_MSI_INTR2_BASE 0x4500
144 #define MSI_INT_STATUS 0x0
145 #define MSI_INT_CLR 0x8
146 #define MSI_INT_MASK_SET 0x10
147 #define MSI_INT_MASK_CLR 0x14
149 #define PCIE_EXT_CFG_DATA 0x8000
150 #define PCIE_EXT_CFG_INDEX 0x9000
152 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
153 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
155 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
156 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
157 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
158 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
160 /* PCIe parameters */
161 #define BRCM_NUM_PCIE_OUT_WINS 0x4
164 #define BRCM_INT_PCI_MSI_SHIFT 0
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
170 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
171 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
174 #define MDIO_PORT0 0x0
175 #define MDIO_DATA_MASK 0x7fffffff
176 #define MDIO_PORT_MASK 0xf0000
177 #define MDIO_REGAD_MASK 0xffff
178 #define MDIO_CMD_MASK 0xfff00000
179 #define MDIO_CMD_READ 0x1
180 #define MDIO_CMD_WRITE 0x0
181 #define MDIO_DATA_DONE_MASK 0x80000000
182 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
183 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
184 #define SSC_REGS_ADDR 0x1100
185 #define SET_ADDR_OFFSET 0x1f
186 #define SSC_CNTL_OFFSET 0x2
187 #define SSC_CNTL_OVRD_EN_MASK 0x8000
188 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
189 #define SSC_STATUS_OFFSET 0x1
190 #define SSC_STATUS_SSC_MASK 0x400
191 #define SSC_STATUS_PLL_LOCK_MASK 0x800
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) argument
195 #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) argument
196 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) argument
197 #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) argument
198 #define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) argument
201 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
202 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
203 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
204 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
205 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
206 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
207 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
208 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
242 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
243 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
269 /* Internal PCIe Host Controller Information.*/
288 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
289 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
296 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
298 return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425; in is_bmips()
303 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
311 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
314 return log2_in - 15; in brcm_pcie_encode_ibar_size()
316 return 0; in brcm_pcie_encode_ibar_size()
321 u32 pkt = 0; in brcm_pcie_mdio_form_pkt()
367 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
373 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
375 if (ret < 0) in brcm_pcie_set_ssc()
378 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
380 if (ret < 0) in brcm_pcie_set_ssc()
385 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
387 if (ret < 0) in brcm_pcie_set_ssc()
391 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
393 if (ret < 0) in brcm_pcie_set_ssc()
399 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
403 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
405 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
406 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
409 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
411 lnkctl2 = (lnkctl2 & ~0xf) | gen; in brcm_pcie_set_gen()
412 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
415 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
425 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
426 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
430 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
432 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
437 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
439 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
447 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
450 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
453 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
456 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
460 .name = "BRCM STB PCIe MSI",
482 dev = msi->dev; in brcm_pcie_msi_isr()
484 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
485 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
487 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
489 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
501 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
502 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
503 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
509 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
511 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
525 mutex_lock(&msi->lock); in brcm_msi_alloc()
526 hwirq = bitmap_find_free_region(msi->used, msi->nr, in brcm_msi_alloc()
528 mutex_unlock(&msi->lock); in brcm_msi_alloc()
536 mutex_lock(&msi->lock); in brcm_msi_free()
537 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); in brcm_msi_free()
538 mutex_unlock(&msi->lock); in brcm_msi_free()
544 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc()
549 if (hwirq < 0) in brcm_irq_domain_alloc()
552 for (i = 0; i < nr_irqs; i++) in brcm_irq_domain_alloc()
554 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
556 return 0; in brcm_irq_domain_alloc()
565 brcm_msi_free(msi, d->hwirq, nr_irqs); in brcm_irq_domain_free()
575 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
576 struct device *dev = msi->dev; in brcm_allocate_domains()
578 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
579 if (!msi->inner_domain) { in brcm_allocate_domains()
581 return -ENOMEM; in brcm_allocate_domains()
584 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
586 msi->inner_domain); in brcm_allocate_domains()
587 if (!msi->msi_domain) { in brcm_allocate_domains()
589 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
590 return -ENOMEM; in brcm_allocate_domains()
593 return 0; in brcm_allocate_domains()
598 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
599 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
602 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
604 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
608 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
614 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
617 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
618 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
621 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
624 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
625 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
626 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
627 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
629 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
630 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
633 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
637 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
639 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
640 if (irq <= 0) { in brcm_pcie_enable_msi()
642 return -ENODEV; in brcm_pcie_enable_msi()
647 return -ENOMEM; in brcm_pcie_enable_msi()
649 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
650 msi->dev = dev; in brcm_pcie_enable_msi()
651 msi->base = pcie->base; in brcm_pcie_enable_msi()
652 msi->np = pcie->np; in brcm_pcie_enable_msi()
653 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
654 msi->irq = irq; in brcm_pcie_enable_msi()
655 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
663 if (msi->legacy) { in brcm_pcie_enable_msi()
664 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); in brcm_pcie_enable_msi()
665 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
666 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
668 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
669 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
670 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
677 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
680 pcie->msi = msi; in brcm_pcie_enable_msi()
682 return 0; in brcm_pcie_enable_msi()
686 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
688 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
694 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
696 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
706 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
707 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
714 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
715 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
719 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
727 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
728 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
735 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
736 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
740 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
741 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
742 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
745 static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
749 int ret = 0; in brcm_pcie_bridge_sw_init_set_generic()
751 if (pcie->bridge_reset) { in brcm_pcie_bridge_sw_init_set_generic()
753 ret = reset_control_assert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
755 ret = reset_control_deassert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
758 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", in brcm_pcie_bridge_sw_init_set_generic()
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
771 static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
776 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
778 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
780 return 0; in brcm_pcie_bridge_sw_init_set_7278()
783 static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
787 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
788 return -EINVAL; in brcm_pcie_perst_set_4908()
791 ret = reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
793 ret = reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
796 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", in brcm_pcie_perst_set_4908()
801 static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
805 /* Perst bit has moved and assert value is 0 */ in brcm_pcie_perst_set_7278()
806 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
808 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
810 return 0; in brcm_pcie_perst_set_7278()
813 static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
817 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
819 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
821 return 0; in brcm_pcie_perst_set_generic()
827 b->size = size; in add_inbound_win()
828 b->cpu_addr = cpu_addr; in add_inbound_win()
829 b->pci_offset = pci_offset; in add_inbound_win()
833 static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, in brcm_pcie_get_inbound_wins() argument
836 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_inbound_wins()
837 u64 pci_offset, cpu_addr, size = 0, tot_size = 0; in brcm_pcie_get_inbound_wins()
839 struct device *dev = pcie->dev; in brcm_pcie_get_inbound_wins()
840 u64 lowest_pcie_addr = ~(u64)0; in brcm_pcie_get_inbound_wins()
841 int ret, i = 0; in brcm_pcie_get_inbound_wins()
842 u8 n = 0; in brcm_pcie_get_inbound_wins()
845 * The HW registers (and PCIe) use order-1 numbering for BARs. As such, in brcm_pcie_get_inbound_wins()
846 * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. in brcm_pcie_get_inbound_wins()
858 if (pcie->soc_base != BCM7712) in brcm_pcie_get_inbound_wins()
859 add_inbound_win(b++, &n, 0, 0, 0); in brcm_pcie_get_inbound_wins()
861 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_inbound_wins()
862 u64 pcie_start = entry->res->start - entry->offset; in brcm_pcie_get_inbound_wins()
863 u64 cpu_start = entry->res->start; in brcm_pcie_get_inbound_wins()
865 size = resource_size(entry->res); in brcm_pcie_get_inbound_wins()
871 * offering a non-overlapping viewport to system memory. in brcm_pcie_get_inbound_wins()
875 if (pcie->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
878 if (n > pcie->num_inbound_wins) in brcm_pcie_get_inbound_wins()
882 if (lowest_pcie_addr == ~(u64)0) { in brcm_pcie_get_inbound_wins()
883 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_inbound_wins()
884 return -EINVAL; in brcm_pcie_get_inbound_wins()
892 if (pcie->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
895 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_inbound_wins()
897 if (ret <= 0) { in brcm_pcie_get_inbound_wins()
899 pcie->num_memc = 1; in brcm_pcie_get_inbound_wins()
900 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
902 pcie->num_memc = ret; in brcm_pcie_get_inbound_wins()
906 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
907 size += pcie->memc_size[i]; in brcm_pcie_get_inbound_wins()
910 size = 1ULL << fls64(size - 1); in brcm_pcie_get_inbound_wins()
914 * of system memory, so we set it to 0. in brcm_pcie_get_inbound_wins()
916 cpu_addr = 0; in brcm_pcie_get_inbound_wins()
921 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_inbound_wins()
923 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_inbound_wins()
924 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_inbound_wins()
925 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_inbound_wins()
926 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_inbound_wins()
929 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_inbound_wins()
932 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_inbound_wins()
934 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_inbound_wins()
935 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_inbound_wins()
942 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_inbound_wins()
943 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_inbound_wins()
947 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_inbound_wins()
948 * region at location 0 (since we have to allow some space for in brcm_pcie_get_inbound_wins()
952 if (!size || (pci_offset & (size - 1)) || in brcm_pcie_get_inbound_wins()
954 dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\n", in brcm_pcie_get_inbound_wins()
956 return -EINVAL; in brcm_pcie_get_inbound_wins()
966 add_inbound_win(b++, &n, 0, 0, 0); in brcm_pcie_get_inbound_wins()
974 return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); in brcm_bar_reg_offset()
976 return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); in brcm_bar_reg_offset()
982 return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); in brcm_ubus_reg_offset()
984 return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); in brcm_ubus_reg_offset()
987 static void set_inbound_win_registers(struct brcm_pcie *pcie, in set_inbound_win_registers() argument
991 void __iomem *base = pcie->base; in set_inbound_win_registers()
1015 if (pcie->soc_base == BCM7712) { in set_inbound_win_registers()
1018 tmp = lower_32_bits(cpu_addr) & ~0xfff; in set_inbound_win_registers()
1027 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
1030 void __iomem *base = pcie->base; in brcm_pcie_setup()
1034 u8 num_out_wins = 0; in brcm_pcie_setup()
1035 int num_inbound_wins = 0; in brcm_pcie_setup()
1039 ret = pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
1044 if (pcie->soc_base == BCM2711) { in brcm_pcie_setup()
1045 ret = pcie->perst_set(pcie, 1); in brcm_pcie_setup()
1047 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1055 ret = pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1059 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_setup()
1060 if (is_bmips(pcie)) in brcm_pcie_setup()
1064 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_setup()
1070 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
1071 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
1073 if (is_bmips(pcie)) in brcm_pcie_setup()
1074 burst = 0x1; /* 256 bytes */ in brcm_pcie_setup()
1075 else if (pcie->soc_base == BCM2711) in brcm_pcie_setup()
1076 burst = 0x0; /* 128 bytes */ in brcm_pcie_setup()
1077 else if (pcie->soc_base == BCM7278) in brcm_pcie_setup()
1078 burst = 0x3; /* 512 bytes */ in brcm_pcie_setup()
1080 burst = 0x2; /* 512 bytes */ in brcm_pcie_setup()
1094 num_inbound_wins = brcm_pcie_get_inbound_wins(pcie, inbound_wins); in brcm_pcie_setup()
1095 if (num_inbound_wins < 0) in brcm_pcie_setup()
1098 set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); in brcm_pcie_setup()
1100 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
1101 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
1102 return -EINVAL; in brcm_pcie_setup()
1106 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1107 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
1109 if (memc == 0) in brcm_pcie_setup()
1110 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); in brcm_pcie_setup()
1123 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
1127 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
1129 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
1132 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
1134 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1143 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1146 u32p_replace_bits(&tmp, 0x060400, in brcm_pcie_setup()
1150 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
1151 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
1152 struct resource *res = entry->res; in brcm_pcie_setup()
1158 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1159 return -EINVAL; in brcm_pcie_setup()
1162 if (is_bmips(pcie)) { in brcm_pcie_setup()
1163 u64 start = res->start; in brcm_pcie_setup()
1166 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1169 for (j = 0; j < nwins; j++, start += SZ_128M) in brcm_pcie_setup()
1170 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1171 start - entry->offset, in brcm_pcie_setup()
1175 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1176 res->start - entry->offset, in brcm_pcie_setup()
1181 /* PCIe->SCB endian mode for inbound window */ in brcm_pcie_setup()
1187 return 0; in brcm_pcie_setup()
1193 * presence of a PCIe access.
1195 static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) in brcm_extend_rbus_timeout() argument
1198 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1202 if (pcie->soc_base == BCM7712) in brcm_extend_rbus_timeout()
1206 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1209 static void brcm_config_clkreq(struct brcm_pcie *pcie) in brcm_config_clkreq() argument
1211 static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; in brcm_config_clkreq()
1216 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1217 if (ret && ret != -EINVAL) { in brcm_config_clkreq()
1218 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1223 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1226 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1228 * "no-l1ss" -- Provides Clock Power Management, L0s, and in brcm_config_clkreq()
1231 * L1SS capable AND the OS enables L1SS, all PCIe traffic in brcm_config_clkreq()
1236 * We want to un-advertise L1 substates because if the OS in brcm_config_clkreq()
1239 * "no-l1ss" mode. in brcm_config_clkreq()
1241 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1243 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1245 } else if (strcmp(mode, "default") == 0) { in brcm_config_clkreq()
1247 * "default" -- Provides L0s, L1, and L1SS, but not in brcm_config_clkreq()
1251 * section 3.2.5.2.2 of the PCIe spec. This situation is in brcm_config_clkreq()
1255 brcm_extend_rbus_timeout(pcie); in brcm_config_clkreq()
1259 * "safe" -- No power savings; refclk is driven by RC in brcm_config_clkreq()
1262 if (strcmp(mode, "safe") != 0) in brcm_config_clkreq()
1263 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1266 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1268 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1271 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1273 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1274 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1280 if (pcie->gen) in brcm_pcie_start_link()
1281 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1284 ret = pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1289 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification in brcm_pcie_start_link()
1290 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1296 * configure RC. Intermittently check status for link-up, up to a in brcm_pcie_start_link()
1299 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1302 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1304 return -ENODEV; in brcm_pcie_start_link()
1307 brcm_config_clkreq(pcie); in brcm_pcie_start_link()
1309 if (pcie->ssc) { in brcm_pcie_start_link()
1310 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1311 if (ret == 0) in brcm_pcie_start_link()
1324 return 0; in brcm_pcie_start_link()
1342 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1343 for (i = 0; i < ARRAY_SIZE(supplies); i++) in alloc_subdev_regulators()
1344 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1352 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1353 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1357 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1358 return 0; in brcm_pcie_add_bus()
1360 if (dev->of_node) { in brcm_pcie_add_bus()
1367 pcie->sr = sr; in brcm_pcie_add_bus()
1369 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1372 pcie->sr = NULL; in brcm_pcie_add_bus()
1376 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1379 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1380 pcie->sr = NULL; in brcm_pcie_add_bus()
1385 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1386 return 0; in brcm_pcie_add_bus()
1391 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1392 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1393 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1395 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_remove_bus()
1398 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1400 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1401 pcie->sr = NULL; in brcm_pcie_remove_bus()
1404 /* L23 is a low-power PCIe link state */
1405 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1407 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1419 for (i = 0; i < 15 && !l23; i++) { in brcm_pcie_enter_l23()
1427 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1430 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1440 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1441 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1442 u32 tmp, combined_mask = 0; in brcm_phy_cntl()
1444 void __iomem *base = pcie->base; in brcm_phy_cntl()
1447 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1448 val = start ? BIT_MASK(shifts[i]) : 0; in brcm_phy_cntl()
1457 val = start ? combined_mask : 0; in brcm_phy_cntl()
1459 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1461 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1466 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1468 return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1471 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1473 return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1476 static int brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1478 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1481 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1482 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1484 ret = pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1490 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_turn_off()
1494 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_turn_off()
1496 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_turn_off()
1498 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1499 ret = pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1508 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1510 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1517 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1518 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1521 ret = brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1530 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1533 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1539 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1542 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1545 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1546 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1547 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1548 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1549 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1550 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1553 rret = reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1561 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1563 return 0; in brcm_pcie_suspend_noirq()
1568 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1573 base = pcie->base; in brcm_pcie_resume_noirq()
1574 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1578 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1582 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1587 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1589 /* SERDES_IDDQ = 0 */ in brcm_pcie_resume_noirq()
1590 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_resume_noirq()
1591 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_resume_noirq()
1592 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_resume_noirq()
1597 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1601 if (pcie->sr) { in brcm_pcie_resume_noirq()
1602 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1609 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1611 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1612 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1620 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1624 if (pcie->msi) in brcm_pcie_resume_noirq()
1625 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1627 return 0; in brcm_pcie_resume_noirq()
1630 if (pcie->sr) in brcm_pcie_resume_noirq()
1631 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1633 rret = reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1635 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); in brcm_pcie_resume_noirq()
1637 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1641 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1643 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1644 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1645 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1646 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1647 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1648 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1649 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1654 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1655 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1657 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1658 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1659 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1663 [RGR1_SW_INIT_1] = 0x9210,
1664 [EXT_CFG_INDEX] = 0x9000,
1665 [EXT_CFG_DATA] = 0x9004,
1666 [PCIE_HARD_DEBUG] = 0x4204,
1667 [PCIE_INTR2_CPU_BASE] = 0x4300,
1671 [RGR1_SW_INIT_1] = 0xc010,
1672 [EXT_CFG_INDEX] = 0x9000,
1673 [EXT_CFG_DATA] = 0x9004,
1674 [PCIE_HARD_DEBUG] = 0x4204,
1675 [PCIE_INTR2_CPU_BASE] = 0x4300,
1679 [RGR1_SW_INIT_1] = 0x8010,
1680 [EXT_CFG_INDEX] = 0x8300,
1681 [EXT_CFG_DATA] = 0x8304,
1682 [PCIE_HARD_DEBUG] = 0x4204,
1683 [PCIE_INTR2_CPU_BASE] = 0x4300,
1687 [EXT_CFG_INDEX] = 0x9000,
1688 [EXT_CFG_DATA] = 0x9004,
1689 [PCIE_HARD_DEBUG] = 0x4304,
1690 [PCIE_INTR2_CPU_BASE] = 0x4400,
1759 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1760 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1761 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1762 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1763 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1764 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1765 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1766 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1767 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1789 struct device_node *np = pdev->dev.of_node; in brcm_pcie_probe()
1792 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1795 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1797 return -ENOMEM; in brcm_pcie_probe()
1799 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1802 return -EINVAL; in brcm_pcie_probe()
1805 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1806 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1807 pcie->np = np; in brcm_pcie_probe()
1808 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1809 pcie->soc_base = data->soc_base; in brcm_pcie_probe()
1810 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1811 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1812 pcie->has_phy = data->has_phy; in brcm_pcie_probe()
1813 pcie->num_inbound_wins = data->num_inbound_wins; in brcm_pcie_probe()
1815 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1816 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1817 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1819 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1820 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1821 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1824 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1826 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1828 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1829 if (IS_ERR(pcie->rescal)) in brcm_pcie_probe()
1830 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1832 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1833 if (IS_ERR(pcie->perst_reset)) in brcm_pcie_probe()
1834 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1836 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); in brcm_pcie_probe()
1837 if (IS_ERR(pcie->bridge_reset)) in brcm_pcie_probe()
1838 return PTR_ERR(pcie->bridge_reset); in brcm_pcie_probe()
1840 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); in brcm_pcie_probe()
1841 if (IS_ERR(pcie->swinit_reset)) in brcm_pcie_probe()
1842 return PTR_ERR(pcie->swinit_reset); in brcm_pcie_probe()
1844 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1846 return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); in brcm_pcie_probe()
1848 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1850 if (pcie->swinit_reset) { in brcm_pcie_probe()
1851 ret = reset_control_assert(pcie->swinit_reset); in brcm_pcie_probe()
1853 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1854 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1861 ret = reset_control_deassert(pcie->swinit_reset); in brcm_pcie_probe()
1863 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1864 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1865 "could not de-assert reset 'swinit'\n"); in brcm_pcie_probe()
1869 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1871 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1872 return dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1875 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1877 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1878 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1882 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1886 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1887 if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1888 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1889 ret = -ENODEV; in brcm_pcie_probe()
1894 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1896 if (msi_np == pcie->np) in brcm_pcie_probe()
1897 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1902 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1907 bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1908 bridge->sysdata = pcie; in brcm_pcie_probe()
1910 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1913 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1914 ret = -ENODEV; in brcm_pcie_probe()
1921 return 0; in brcm_pcie_probe()
1924 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1940 .name = "brcm-pcie",
1948 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");