Lines Matching +full:0 +full:x4048
38 #define BRCM_PCIE_CAP_REGS 0x00ac
41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
43 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
45 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
46 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
48 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
51 #define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
52 #define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
54 #define PCIE_RC_DL_MDIO_ADDR 0x1100
55 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
56 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
58 #define PCIE_MISC_MISC_CTRL 0x4008
59 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
60 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
61 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
62 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
63 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
65 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
66 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
67 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
70 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
74 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
86 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
87 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
89 #define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
92 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
93 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
95 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
96 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
97 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
99 #define PCIE_MISC_PCIE_CTRL 0x4064
100 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
101 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
103 #define PCIE_MISC_PCIE_STATUS 0x4068
104 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
105 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
106 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
107 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
109 #define PCIE_MISC_REVISION 0x406c
110 #define BRCM_PCIE_HW_REV_33 0x0303
111 #define BRCM_PCIE_HW_REV_3_20 0x0320
113 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
114 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
115 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
119 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
120 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
124 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
125 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
129 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
130 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
131 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
132 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
137 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
138 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0)
139 #define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c
141 #define PCIE_MSI_INTR2_BASE 0x4500
144 #define MSI_INT_STATUS 0x0
145 #define MSI_INT_CLR 0x8
146 #define MSI_INT_MASK_SET 0x10
147 #define MSI_INT_MASK_CLR 0x14
149 #define PCIE_EXT_CFG_DATA 0x8000
150 #define PCIE_EXT_CFG_INDEX 0x9000
152 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
153 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
155 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
156 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
157 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
158 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
161 #define BRCM_NUM_PCIE_OUT_WINS 0x4
164 #define BRCM_INT_PCI_MSI_SHIFT 0
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
170 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
171 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
174 #define MDIO_PORT0 0x0
175 #define MDIO_DATA_MASK 0x7fffffff
176 #define MDIO_PORT_MASK 0xf0000
177 #define MDIO_REGAD_MASK 0xffff
178 #define MDIO_CMD_MASK 0xfff00000
179 #define MDIO_CMD_READ 0x1
180 #define MDIO_CMD_WRITE 0x0
181 #define MDIO_DATA_DONE_MASK 0x80000000
182 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
183 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
184 #define SSC_REGS_ADDR 0x1100
185 #define SET_ADDR_OFFSET 0x1f
186 #define SSC_CNTL_OFFSET 0x2
187 #define SSC_CNTL_OVRD_EN_MASK 0x8000
188 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
189 #define SSC_STATUS_OFFSET 0x1
190 #define SSC_STATUS_SSC_MASK 0x400
191 #define SSC_STATUS_PLL_LOCK_MASK 0x800
201 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
202 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
203 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
204 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
205 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
206 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
207 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
208 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
311 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
316 return 0; in brcm_pcie_encode_ibar_size()
321 u32 pkt = 0; in brcm_pcie_mdio_form_pkt()
375 if (ret < 0) in brcm_pcie_set_ssc()
380 if (ret < 0) in brcm_pcie_set_ssc()
387 if (ret < 0) in brcm_pcie_set_ssc()
393 if (ret < 0) in brcm_pcie_set_ssc()
399 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
411 lnkctl2 = (lnkctl2 & ~0xf) | gen; in brcm_pcie_set_gen()
503 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
549 if (hwirq < 0) in brcm_irq_domain_alloc()
552 for (i = 0; i < nr_irqs; i++) in brcm_irq_domain_alloc()
556 return 0; in brcm_irq_domain_alloc()
593 return 0; in brcm_allocate_domains()
621 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
624 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
640 if (irq <= 0) { in brcm_pcie_enable_msi()
670 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
682 return 0; in brcm_pcie_enable_msi()
719 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
749 int ret = 0; in brcm_pcie_bridge_sw_init_set_generic()
780 return 0; in brcm_pcie_bridge_sw_init_set_7278()
805 /* Perst bit has moved and assert value is 0 */ in brcm_pcie_perst_set_7278()
810 return 0; in brcm_pcie_perst_set_7278()
821 return 0; in brcm_pcie_perst_set_generic()
837 u64 pci_offset, cpu_addr, size = 0, tot_size = 0; in brcm_pcie_get_inbound_wins()
840 u64 lowest_pcie_addr = ~(u64)0; in brcm_pcie_get_inbound_wins()
841 int ret, i = 0; in brcm_pcie_get_inbound_wins()
842 u8 n = 0; in brcm_pcie_get_inbound_wins()
846 * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. in brcm_pcie_get_inbound_wins()
859 add_inbound_win(b++, &n, 0, 0, 0); in brcm_pcie_get_inbound_wins()
882 if (lowest_pcie_addr == ~(u64)0) { in brcm_pcie_get_inbound_wins()
897 if (ret <= 0) { in brcm_pcie_get_inbound_wins()
900 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
906 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
914 * of system memory, so we set it to 0. in brcm_pcie_get_inbound_wins()
916 cpu_addr = 0; in brcm_pcie_get_inbound_wins()
948 * region at location 0 (since we have to allow some space for in brcm_pcie_get_inbound_wins()
954 dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\n", in brcm_pcie_get_inbound_wins()
966 add_inbound_win(b++, &n, 0, 0, 0); in brcm_pcie_get_inbound_wins()
1018 tmp = lower_32_bits(cpu_addr) & ~0xfff; in set_inbound_win_registers()
1034 u8 num_out_wins = 0; in brcm_pcie_setup()
1035 int num_inbound_wins = 0; in brcm_pcie_setup()
1047 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1055 ret = pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1070 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
1071 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
1074 burst = 0x1; /* 256 bytes */ in brcm_pcie_setup()
1076 burst = 0x0; /* 128 bytes */ in brcm_pcie_setup()
1078 burst = 0x3; /* 512 bytes */ in brcm_pcie_setup()
1080 burst = 0x2; /* 512 bytes */ in brcm_pcie_setup()
1095 if (num_inbound_wins < 0) in brcm_pcie_setup()
1106 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1109 if (memc == 0) in brcm_pcie_setup()
1110 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); in brcm_pcie_setup()
1146 u32p_replace_bits(&tmp, 0x060400, in brcm_pcie_setup()
1169 for (j = 0; j < nwins; j++, start += SZ_128M) in brcm_pcie_setup()
1187 return 0; in brcm_pcie_setup()
1226 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1245 } else if (strcmp(mode, "default") == 0) { in brcm_config_clkreq()
1262 if (strcmp(mode, "safe") != 0) in brcm_config_clkreq()
1284 ret = pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1290 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1299 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1311 if (ret == 0) in brcm_pcie_start_link()
1324 return 0; in brcm_pcie_start_link()
1343 for (i = 0; i < ARRAY_SIZE(supplies); i++) in alloc_subdev_regulators()
1358 return 0; in brcm_pcie_add_bus()
1386 return 0; in brcm_pcie_add_bus()
1419 for (i = 0; i < 15 && !l23; i++) { in brcm_pcie_enter_l23()
1440 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1442 u32 tmp, combined_mask = 0; in brcm_phy_cntl()
1448 val = start ? BIT_MASK(shifts[i]) : 0; in brcm_phy_cntl()
1457 val = start ? combined_mask : 0; in brcm_phy_cntl()
1459 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1468 return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1473 return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1490 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_turn_off()
1563 return 0; in brcm_pcie_suspend_noirq()
1587 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1589 /* SERDES_IDDQ = 0 */ in brcm_pcie_resume_noirq()
1591 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_resume_noirq()
1627 return 0; in brcm_pcie_resume_noirq()
1663 [RGR1_SW_INIT_1] = 0x9210,
1664 [EXT_CFG_INDEX] = 0x9000,
1665 [EXT_CFG_DATA] = 0x9004,
1666 [PCIE_HARD_DEBUG] = 0x4204,
1667 [PCIE_INTR2_CPU_BASE] = 0x4300,
1671 [RGR1_SW_INIT_1] = 0xc010,
1672 [EXT_CFG_INDEX] = 0x9000,
1673 [EXT_CFG_DATA] = 0x9004,
1674 [PCIE_HARD_DEBUG] = 0x4204,
1675 [PCIE_INTR2_CPU_BASE] = 0x4300,
1679 [RGR1_SW_INIT_1] = 0x8010,
1680 [EXT_CFG_INDEX] = 0x8300,
1681 [EXT_CFG_DATA] = 0x8304,
1682 [PCIE_HARD_DEBUG] = 0x4204,
1683 [PCIE_INTR2_CPU_BASE] = 0x4300,
1687 [EXT_CFG_INDEX] = 0x9000,
1688 [EXT_CFG_DATA] = 0x9004,
1689 [PCIE_HARD_DEBUG] = 0x4304,
1690 [PCIE_INTR2_CPU_BASE] = 0x4400,
1815 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1824 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1848 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1894 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1921 return 0; in brcm_pcie_probe()