36 #define V3_PCI_VENDOR			0x00000000
37 #define V3_PCI_DEVICE			0x00000002
38 #define V3_PCI_CMD			0x00000004
39 #define V3_PCI_STAT			0x00000006
40 #define V3_PCI_CC_REV			0x00000008
41 #define V3_PCI_HDR_CFG			0x0000000C
42 #define V3_PCI_IO_BASE			0x00000010
43 #define V3_PCI_BASE0			0x00000014
44 #define V3_PCI_BASE1			0x00000018
45 #define V3_PCI_SUB_VENDOR		0x0000002C
46 #define V3_PCI_SUB_ID			0x0000002E
47 #define V3_PCI_ROM			0x00000030
48 #define V3_PCI_BPARAM			0x0000003C
49 #define V3_PCI_MAP0			0x00000040
50 #define V3_PCI_MAP1			0x00000044
51 #define V3_PCI_INT_STAT			0x00000048
52 #define V3_PCI_INT_CFG			0x0000004C
53 #define V3_LB_BASE0			0x00000054
54 #define V3_LB_BASE1			0x00000058
55 #define V3_LB_MAP0			0x0000005E
56 #define V3_LB_MAP1			0x00000062
57 #define V3_LB_BASE2			0x00000064
58 #define V3_LB_MAP2			0x00000066
59 #define V3_LB_SIZE			0x00000068
60 #define V3_LB_IO_BASE			0x0000006E
61 #define V3_FIFO_CFG			0x00000070
62 #define V3_FIFO_PRIORITY		0x00000072
63 #define V3_FIFO_STAT			0x00000074
64 #define V3_LB_ISTAT			0x00000076
65 #define V3_LB_IMASK			0x00000077
66 #define V3_SYSTEM			0x00000078
67 #define V3_LB_CFG			0x0000007A
68 #define V3_PCI_CFG			0x0000007C
69 #define V3_DMA_PCI_ADR0			0x00000080
70 #define V3_DMA_PCI_ADR1			0x00000090
71 #define V3_DMA_LOCAL_ADR0		0x00000084
72 #define V3_DMA_LOCAL_ADR1		0x00000094
73 #define V3_DMA_LENGTH0			0x00000088
74 #define V3_DMA_LENGTH1			0x00000098
75 #define V3_DMA_CSR0			0x0000008B
76 #define V3_DMA_CSR1			0x0000009B
77 #define V3_DMA_CTLB_ADR0		0x0000008C
78 #define V3_DMA_CTLB_ADR1		0x0000009C
79 #define V3_DMA_DELAY			0x000000E0
80 #define V3_MAIL_DATA			0x000000C0
81 #define V3_PCI_MAIL_IEWR		0x000000D0
82 #define V3_PCI_MAIL_IERD		0x000000D2
83 #define V3_LB_MAIL_IEWR			0x000000D4
84 #define V3_LB_MAIL_IERD			0x000000D6
85 #define V3_MAIL_WR_STAT			0x000000D8
86 #define V3_MAIL_RD_STAT			0x000000DA
87 #define V3_QBA_MAP			0x000000DC
103 #define V3_LB_ISTAT_DMA0		BIT(0)
111 #define V3_COMMAND_M_IO_EN		BIT(0)
116 #define V3_SYSTEM_UNLOCK		0xa05f
127  * This is the value applied to C/BE[3:1], with bit 0 always held 0
132 #define V3_PCI_CFG_TYPE_DEFAULT		0x3
135 #define V3_PCI_BASE_M_ADR_BASE		0xFFF00000U
136 #define V3_PCI_BASE_M_ADR_BASEL		0x000FFF00U
139 #define V3_PCI_BASE_M_IO		BIT(0)
142 #define V3_PCI_MAP_M_MAP_ADR		0xFFF00000U
146 #define V3_PCI_MAP_M_ADR_SIZE		0x000000F0U
148 #define V3_PCI_MAP_M_ENABLE		BIT(0)
151 #define V3_LB_BASE_ADR_BASE		0xfff00000U
155 #define V3_LB_BASE_ENABLE		BIT(0)
157 #define V3_LB_BASE_ADR_SIZE_1MB		(0 << 4)
173 #define V3_LB_MAP_MAP_ADR		0xfff0U
175 #define V3_LB_MAP_AD_LOW_EN		BIT(0)
177 #define V3_LB_MAP_TYPE_IACK		(0 << 1)
186 #define V3_LB_BASE2_ADR_BASE		0xff00U
188 #define V3_LB_BASE2_ENABLE		BIT(0)
193 #define V3_LB_MAP2_MAP_ADR		0xff00U
209 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB	BIT(0)
211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY	(BIT(0)|BIT(1))
214 #define V3_LB_CFG_LB_TO_64_CYCLES	0x0000
230 #define INTEGRATOR_SC_PCI_OFFSET	0x18
231 #define INTEGRATOR_SC_PCI_ENABLE	BIT(0)
233 #define INTEGRATOR_SC_LBFADDR_OFFSET	0x20
234 #define INTEGRATOR_SC_LBFCODE_OFFSET	0x24
317 	if (busnr == 0) {  in v3_map_bus()
321 		 * local bus segment so need a type 0 config cycle  in v3_map_bus()
328 		 *  0   = PCI A1 & A0 are 0 (0)  in v3_map_bus()
350 		 *  10:8  = func number (2:0 of devfn)  in v3_map_bus()
354 		 *  0   = PCI A1 & A0 from host bus (1)  in v3_map_bus()
409 		"[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",  in v3_pci_read_config()
423 		"[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",  in v3_pci_write_config()
469 		dev_info(dev, "DMA channel 0 interrupt\n");  in v3_irq()
471 	writeb(0, v3->base + V3_LB_ISTAT);  in v3_irq()
502 		writel(0x6200, v3->base + V3_LB_IO_BASE);  in v3_integrator_init()
506 			writeb(0xaa, v3->base + V3_MAIL_DATA);  in v3_integrator_init()
507 			writeb(0x55, v3->base + V3_MAIL_DATA + 4);  in v3_integrator_init()
508 		} while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&  in v3_integrator_init()
509 			 readb(v3->base + V3_MAIL_DATA) != 0x55);  in v3_integrator_init()
514 	return 0;  in v3_integrator_init()
574 			/* Setup window 0 - PCI non-prefetchable memory */  in v3_pci_setup_resource()
592 	return 0;  in v3_pci_setup_resource()
664 		"DMA MEM CPU: 0x%016llx -> 0x%016llx => "  in v3_get_dma_range_config()
665 		"PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",  in v3_get_dma_range_config()
670 	return 0;  in v3_get_dma_range_config()
679 	int i = 0;  in v3_pci_parse_map_dma_ranges()
689 		if (i == 0) {  in v3_pci_parse_map_dma_ranges()
701 	return 0;  in v3_pci_parse_map_dma_ranges()
738 	v3->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);  in v3_pci_probe()
762 	irq = platform_get_irq(pdev, 0);  in v3_pci_probe()
763 	if (irq < 0)  in v3_pci_probe()
766 	ret = devm_request_irq(dev, irq, v3_irq, 0,  in v3_pci_probe()
768 	if (ret < 0) {  in v3_pci_probe()
826 	writel(0x00000000, v3->base + V3_PCI_IO_BASE);  in v3_pci_probe()
852 	writeb(0, v3->base + V3_LB_ISTAT);  in v3_pci_probe()
872 	writeb(0, v3->base + V3_LB_ISTAT);  in v3_pci_probe()