1 // SPDX-License-Identifier: GPL-2.0
3  * PCIe host controller driver for Mobiveil PCIe Host controller
6  * Copyright 2019-2020 NXP
25 #include "pcie-mobiveil.h"
37 	if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0))  in mobiveil_pcie_valid_device()
44  * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 	struct mobiveil_pcie *pcie = bus->sysdata;  in mobiveil_pcie_map_bus()  local
51 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_map_bus()
59 		return pcie->csr_axi_slave_base + where;  in mobiveil_pcie_map_bus()
67 	value = bus->number << PAB_BUS_SHIFT |  in mobiveil_pcie_map_bus()
71 	mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));  in mobiveil_pcie_map_bus()
73 	return rp->config_axi_slave_base + where;  in mobiveil_pcie_map_bus()
85 	struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);  in mobiveil_pcie_isr()  local
86 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_isr()
87 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_isr()
88 	struct mobiveil_msi *msi = &rp->msi;  in mobiveil_pcie_isr()
102 	val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
103 	mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_pcie_isr()
108 		shifted_status = mobiveil_csr_readl(pcie,  in mobiveil_pcie_isr()
115 				ret = generic_handle_domain_irq(rp->intx_domain,  in mobiveil_pcie_isr()
116 								bit + 1);  in mobiveil_pcie_isr()
122 				mobiveil_csr_writel(pcie,  in mobiveil_pcie_isr()
123 						    1 << (PAB_INTX_START + bit),  in mobiveil_pcie_isr()
127 			shifted_status = mobiveil_csr_readl(pcie,  in mobiveil_pcie_isr()
135 	msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);  in mobiveil_pcie_isr()
138 	while (msi_status & 1) {  in mobiveil_pcie_isr()
139 		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);  in mobiveil_pcie_isr()
147 		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
149 		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
154 		generic_handle_domain_irq(msi->dev_domain, msi_data);  in mobiveil_pcie_isr()
156 		msi_status = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
161 	mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
165 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)  in mobiveil_pcie_parse_dt()  argument
167 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_parse_dt()
168 	struct platform_device *pdev = pcie->pdev;  in mobiveil_pcie_parse_dt()
169 	struct device_node *node = dev->of_node;  in mobiveil_pcie_parse_dt()
170 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_parse_dt()
176 	rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
177 	if (IS_ERR(rp->config_axi_slave_base))  in mobiveil_pcie_parse_dt()
178 		return PTR_ERR(rp->config_axi_slave_base);  in mobiveil_pcie_parse_dt()
179 	rp->ob_io_res = res;  in mobiveil_pcie_parse_dt()
184 	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
185 	if (IS_ERR(pcie->csr_axi_slave_base))  in mobiveil_pcie_parse_dt()
186 		return PTR_ERR(pcie->csr_axi_slave_base);  in mobiveil_pcie_parse_dt()
187 	pcie->pcie_reg_base = res->start;  in mobiveil_pcie_parse_dt()
190 	if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))  in mobiveil_pcie_parse_dt()
191 		pcie->apio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
193 	if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))  in mobiveil_pcie_parse_dt()
194 		pcie->ppio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
199 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  in mobiveil_pcie_enable_msi()  argument
201 	phys_addr_t msg_addr = pcie->pcie_reg_base;  in mobiveil_pcie_enable_msi()
202 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_pcie_enable_msi()
204 	msi->num_of_vectors = PCI_NUM_MSI;  in mobiveil_pcie_enable_msi()
205 	msi->msi_pages_phys = (phys_addr_t)msg_addr;  in mobiveil_pcie_enable_msi()
208 		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);  in mobiveil_pcie_enable_msi()
210 		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);  in mobiveil_pcie_enable_msi()
211 	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);  in mobiveil_pcie_enable_msi()
212 	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  in mobiveil_pcie_enable_msi()
215 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)  in mobiveil_host_init()  argument
217 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_host_init()
218 	struct pci_host_bridge *bridge = rp->bridge;  in mobiveil_host_init()
222 	pcie->ib_wins_configured = 0;  in mobiveil_host_init()
223 	pcie->ob_wins_configured = 0;  in mobiveil_host_init()
227 		value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);  in mobiveil_host_init()
230 		mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);  in mobiveil_host_init()
237 	value = mobiveil_csr_readl(pcie, PCI_COMMAND);  in mobiveil_host_init()
239 	mobiveil_csr_writel(pcie, value, PCI_COMMAND);  in mobiveil_host_init()
242 	 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL  in mobiveil_host_init()
245 	pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);  in mobiveil_host_init()
246 	pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);  in mobiveil_host_init()
247 	mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);  in mobiveil_host_init()
250 	 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in  in mobiveil_host_init()
253 	value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
255 	mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
257 	/* Enable PCIe PIO master */  in mobiveil_host_init()
258 	value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);  in mobiveil_host_init()
259 	value |= 1 << PIO_ENABLE_SHIFT;  in mobiveil_host_init()
260 	mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);  in mobiveil_host_init()
270 	program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,  in mobiveil_host_init()
271 			   CFG_WINDOW_TYPE, resource_size(rp->ob_io_res));  in mobiveil_host_init()
274 	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);  in mobiveil_host_init()
277 	resource_list_for_each_entry(win, &bridge->windows) {  in mobiveil_host_init()
278 		if (resource_type(win->res) == IORESOURCE_MEM)  in mobiveil_host_init()
280 		else if (resource_type(win->res) == IORESOURCE_IO)  in mobiveil_host_init()
286 		program_ob_windows(pcie, pcie->ob_wins_configured,  in mobiveil_host_init()
287 				   win->res->start,  in mobiveil_host_init()
288 				   win->res->start - win->offset,  in mobiveil_host_init()
289 				   type, resource_size(win->res));  in mobiveil_host_init()
292 	/* fixup for PCIe class register */  in mobiveil_host_init()
293 	value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
296 	mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
303 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_mask_intx_irq()  local
308 	rp = &pcie->rp;  in mobiveil_mask_intx_irq()
309 	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);  in mobiveil_mask_intx_irq()
310 	raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
311 	shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
313 	mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
314 	raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
319 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_unmask_intx_irq()  local
324 	rp = &pcie->rp;  in mobiveil_unmask_intx_irq()
325 	mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);  in mobiveil_unmask_intx_irq()
326 	raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
327 	shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
329 	mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
330 	raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
346 	irq_set_chip_data(irq, domain->host_data);  in mobiveil_pcie_intx_map()
357 	.name = "Mobiveil PCIe MSI",
370 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_compose_msi_msg()  local
371 	phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));  in mobiveil_compose_msi_msg()
373 	msg->address_lo = lower_32_bits(addr);  in mobiveil_compose_msi_msg()
374 	msg->address_hi = upper_32_bits(addr);  in mobiveil_compose_msi_msg()
375 	msg->data = data->hwirq;  in mobiveil_compose_msi_msg()
377 	dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",  in mobiveil_compose_msi_msg()
378 		(int)data->hwirq, msg->address_hi, msg->address_lo);  in mobiveil_compose_msi_msg()
390 	struct mobiveil_pcie *pcie = domain->host_data;  in mobiveil_irq_msi_domain_alloc()  local
391 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_alloc()
394 	WARN_ON(nr_irqs != 1);  in mobiveil_irq_msi_domain_alloc()
395 	mutex_lock(&msi->lock);  in mobiveil_irq_msi_domain_alloc()
397 	bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);  in mobiveil_irq_msi_domain_alloc()
398 	if (bit >= msi->num_of_vectors) {  in mobiveil_irq_msi_domain_alloc()
399 		mutex_unlock(&msi->lock);  in mobiveil_irq_msi_domain_alloc()
400 		return -ENOSPC;  in mobiveil_irq_msi_domain_alloc()
403 	set_bit(bit, msi->msi_irq_in_use);  in mobiveil_irq_msi_domain_alloc()
405 	mutex_unlock(&msi->lock);  in mobiveil_irq_msi_domain_alloc()
408 			    domain->host_data, handle_level_irq, NULL, NULL);  in mobiveil_irq_msi_domain_alloc()
417 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);  in mobiveil_irq_msi_domain_free()  local
418 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_free()
420 	mutex_lock(&msi->lock);  in mobiveil_irq_msi_domain_free()
422 	if (!test_bit(d->hwirq, msi->msi_irq_in_use))  in mobiveil_irq_msi_domain_free()
423 		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",  in mobiveil_irq_msi_domain_free()
424 			d->hwirq);  in mobiveil_irq_msi_domain_free()
426 		__clear_bit(d->hwirq, msi->msi_irq_in_use);  in mobiveil_irq_msi_domain_free()
428 	mutex_unlock(&msi->lock);  in mobiveil_irq_msi_domain_free()
435 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)  in mobiveil_allocate_msi_domains()  argument
437 	struct device *dev = &pcie->pdev->dev;  in mobiveil_allocate_msi_domains()
438 	struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);  in mobiveil_allocate_msi_domains()
439 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_allocate_msi_domains()
441 	mutex_init(&msi->lock);  in mobiveil_allocate_msi_domains()
442 	msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,  in mobiveil_allocate_msi_domains()
443 						&msi_domain_ops, pcie);  in mobiveil_allocate_msi_domains()
444 	if (!msi->dev_domain) {  in mobiveil_allocate_msi_domains()
446 		return -ENOMEM;  in mobiveil_allocate_msi_domains()
449 	msi->msi_domain = pci_msi_create_irq_domain(fwnode,  in mobiveil_allocate_msi_domains()
451 						    msi->dev_domain);  in mobiveil_allocate_msi_domains()
452 	if (!msi->msi_domain) {  in mobiveil_allocate_msi_domains()
454 		irq_domain_remove(msi->dev_domain);  in mobiveil_allocate_msi_domains()
455 		return -ENOMEM;  in mobiveil_allocate_msi_domains()
461 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)  in mobiveil_pcie_init_irq_domain()  argument
463 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_init_irq_domain()
464 	struct device_node *node = dev->of_node;  in mobiveil_pcie_init_irq_domain()
465 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_init_irq_domain()
468 	rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,  in mobiveil_pcie_init_irq_domain()
469 						&intx_domain_ops, pcie);  in mobiveil_pcie_init_irq_domain()
471 	if (!rp->intx_domain) {  in mobiveil_pcie_init_irq_domain()
473 		return -ENOMEM;  in mobiveil_pcie_init_irq_domain()
476 	raw_spin_lock_init(&rp->intx_mask_lock);  in mobiveil_pcie_init_irq_domain()
479 	return mobiveil_allocate_msi_domains(pcie);  in mobiveil_pcie_init_irq_domain()
482 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie)  in mobiveil_pcie_integrated_interrupt_init()  argument
484 	struct platform_device *pdev = pcie->pdev;  in mobiveil_pcie_integrated_interrupt_init()
485 	struct device *dev = &pdev->dev;  in mobiveil_pcie_integrated_interrupt_init()
486 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_integrated_interrupt_init()
492 	pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_integrated_interrupt_init()
493 	if (IS_ERR(pcie->apb_csr_base))  in mobiveil_pcie_integrated_interrupt_init()
494 		return PTR_ERR(pcie->apb_csr_base);  in mobiveil_pcie_integrated_interrupt_init()
497 	mobiveil_pcie_enable_msi(pcie);  in mobiveil_pcie_integrated_interrupt_init()
499 	rp->irq = platform_get_irq(pdev, 0);  in mobiveil_pcie_integrated_interrupt_init()
500 	if (rp->irq < 0)  in mobiveil_pcie_integrated_interrupt_init()
501 		return rp->irq;  in mobiveil_pcie_integrated_interrupt_init()
504 	ret = mobiveil_pcie_init_irq_domain(pcie);  in mobiveil_pcie_integrated_interrupt_init()
510 	irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);  in mobiveil_pcie_integrated_interrupt_init()
513 	mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),  in mobiveil_pcie_integrated_interrupt_init()
520 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)  in mobiveil_pcie_interrupt_init()  argument
522 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_interrupt_init()
524 	if (rp->ops->interrupt_init)  in mobiveil_pcie_interrupt_init()
525 		return rp->ops->interrupt_init(pcie);  in mobiveil_pcie_interrupt_init()
527 	return mobiveil_pcie_integrated_interrupt_init(pcie);  in mobiveil_pcie_interrupt_init()
530 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie)  in mobiveil_pcie_is_bridge()  argument
534 	header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE);  in mobiveil_pcie_is_bridge()
540 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)  in mobiveil_pcie_host_probe()  argument
542 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_host_probe()
543 	struct pci_host_bridge *bridge = rp->bridge;  in mobiveil_pcie_host_probe()
544 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_host_probe()
547 	ret = mobiveil_pcie_parse_dt(pcie);  in mobiveil_pcie_host_probe()
553 	if (!mobiveil_pcie_is_bridge(pcie))  in mobiveil_pcie_host_probe()
554 		return -ENODEV;  in mobiveil_pcie_host_probe()
560 	ret = mobiveil_host_init(pcie, false);  in mobiveil_pcie_host_probe()
566 	ret = mobiveil_pcie_interrupt_init(pcie);  in mobiveil_pcie_host_probe()
573 	bridge->sysdata = pcie;  in mobiveil_pcie_host_probe()
574 	bridge->ops = &mobiveil_pcie_ops;  in mobiveil_pcie_host_probe()
576 	ret = mobiveil_bringup_link(pcie);  in mobiveil_pcie_host_probe()
578 		dev_info(dev, "link bring-up failed\n");  in mobiveil_pcie_host_probe()