Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
37 #define PCIE_UL_REG_S_PCIE_MODE 0x00F4
38 #define PCIE_UL_REG_S_PCIE_MODE_EP 0x00
39 #define PCIE_UL_REG_S_PCIE_MODE_RC 0x04
41 #define PCIE_UL_REG_S_PERSTN_CTRL 0x00F8
45 #define PCIE_UL_DIRECT_PERSTN BIT(0)
50 #define PCIE_UL_REG_S_PHY_INIT_02 0x0104
51 #define PCIE_UL_PHY0_SRAM_EXT_LD_DONE BIT(0)
53 #define PCIE_UL_REG_S_PHY_INIT_03 0x0108
54 #define PCIE_UL_PHY0_SRAM_INIT_DONE BIT(0)
56 #define PCIE_UL_REG_S_INT_EVENT_MASK1 0x0138
57 #define PCIE_UL_CFG_PME_INT BIT(0)
70 #define PCIE_UL_REG_S_SB_MON 0x0198
71 #define PCIE_UL_REG_S_SIG_MON 0x019C
72 #define PCIE_UL_CORE_RST_N_MON BIT(0)
74 #define PCIE_UL_REG_V_SII_DBG_00 0x0844
75 #define PCIE_UL_REG_V_SII_GEN_CTRL_01 0x0860
76 #define PCIE_UL_APP_LTSSM_ENABLE BIT(0)
78 #define PCIE_UL_REG_V_PHY_ST_00 0x0864
79 #define PCIE_UL_SMLH_LINK_UP BIT(0)
81 #define PCIE_UL_REG_V_PHY_ST_02 0x0868
82 #define PCIE_UL_S_DETECT_ACT 0x01
83 #define PCIE_UL_S_L0 0x11
85 #define PISMU_CKON_PCIE 0x0038
87 #define PISMU_CKON_PCIE_MSTR_ACLK BIT(0)
89 #define PISMU_RSOFF_PCIE 0x0538
91 #define PISMU_RSOFF_PCIE_PWR_UP_RST_N BIT(0)
93 #define PCIE_MPU_REG_MP_EN 0x0
94 #define MPU_MP_EN_DISABLE BIT(0)
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
113 /* Access registers in PCIe mpu */
114 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_mpu_writel() argument
116 writel_relaxed(val, pcie->mpu_base + reg); in visconti_mpu_writel()
119 static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg) in visconti_mpu_readl() argument
121 return readl_relaxed(pcie->mpu_base + reg); in visconti_mpu_readl()
126 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev); in visconti_pcie_link_up() local
127 void __iomem *addr = pcie->ulreg_base; in visconti_pcie_link_up()
135 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev); in visconti_pcie_start_link() local
136 void __iomem *addr = pcie->ulreg_base; in visconti_pcie_start_link()
140 visconti_ulreg_writel(pcie, PCIE_UL_APP_LTSSM_ENABLE, in visconti_pcie_start_link()
149 visconti_ulreg_writel(pcie, PCIE_UL_S_INT_EVENT_MASK1_ALL, in visconti_pcie_start_link()
153 val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN); in visconti_pcie_start_link()
154 visconti_mpu_writel(pcie, val & ~MPU_MP_EN_DISABLE, in visconti_pcie_start_link()
158 return 0; in visconti_pcie_start_link()
163 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev); in visconti_pcie_stop_link() local
166 val = visconti_ulreg_readl(pcie, PCIE_UL_REG_V_SII_GEN_CTRL_01); in visconti_pcie_stop_link()
168 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_V_SII_GEN_CTRL_01); in visconti_pcie_stop_link()
170 val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN); in visconti_pcie_stop_link()
171 visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN); in visconti_pcie_stop_link()
176 * 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
177 * bus address. This 0x40000000 is also based on io_base from DT.
181 struct dw_pcie_rp *pp = &pci->pp; in visconti_pcie_cpu_addr_fixup()
183 return cpu_addr & ~pp->io_base; in visconti_pcie_cpu_addr_fixup()
196 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev); in visconti_pcie_host_init() local
201 visconti_smu_writel(pcie, in visconti_pcie_host_init()
206 visconti_smu_writel(pcie, PISMU_RSOFF_PCIE_ULREG_RST_N, in visconti_pcie_host_init()
208 visconti_ulreg_writel(pcie, PCIE_UL_REG_S_PCIE_MODE_RC, in visconti_pcie_host_init()
212 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL); in visconti_pcie_host_init()
216 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL); in visconti_pcie_host_init()
219 visconti_smu_writel(pcie, PISMU_RSOFF_PCIE_PWR_UP_RST_N, in visconti_pcie_host_init()
222 addr = pcie->ulreg_base + PCIE_UL_REG_S_PHY_INIT_03; in visconti_pcie_host_init()
229 visconti_ulreg_writel(pcie, PCIE_UL_PHY0_SRAM_EXT_LD_DONE, in visconti_pcie_host_init()
232 addr = pcie->ulreg_base + PCIE_UL_REG_S_SIG_MON; in visconti_pcie_host_init()
243 struct visconti_pcie *pcie) in visconti_get_resources() argument
245 struct device *dev = &pdev->dev; in visconti_get_resources()
247 pcie->ulreg_base = devm_platform_ioremap_resource_byname(pdev, "ulreg"); in visconti_get_resources()
248 if (IS_ERR(pcie->ulreg_base)) in visconti_get_resources()
249 return PTR_ERR(pcie->ulreg_base); in visconti_get_resources()
251 pcie->smu_base = devm_platform_ioremap_resource_byname(pdev, "smu"); in visconti_get_resources()
252 if (IS_ERR(pcie->smu_base)) in visconti_get_resources()
253 return PTR_ERR(pcie->smu_base); in visconti_get_resources()
255 pcie->mpu_base = devm_platform_ioremap_resource_byname(pdev, "mpu"); in visconti_get_resources()
256 if (IS_ERR(pcie->mpu_base)) in visconti_get_resources()
257 return PTR_ERR(pcie->mpu_base); in visconti_get_resources()
259 pcie->refclk = devm_clk_get(dev, "ref"); in visconti_get_resources()
260 if (IS_ERR(pcie->refclk)) in visconti_get_resources()
261 return dev_err_probe(dev, PTR_ERR(pcie->refclk), in visconti_get_resources()
264 pcie->coreclk = devm_clk_get(dev, "core"); in visconti_get_resources()
265 if (IS_ERR(pcie->coreclk)) in visconti_get_resources()
266 return dev_err_probe(dev, PTR_ERR(pcie->coreclk), in visconti_get_resources()
269 pcie->auxclk = devm_clk_get(dev, "aux"); in visconti_get_resources()
270 if (IS_ERR(pcie->auxclk)) in visconti_get_resources()
271 return dev_err_probe(dev, PTR_ERR(pcie->auxclk), in visconti_get_resources()
274 return 0; in visconti_get_resources()
277 static int visconti_add_pcie_port(struct visconti_pcie *pcie, in visconti_add_pcie_port() argument
280 struct dw_pcie *pci = &pcie->pci; in visconti_add_pcie_port()
281 struct dw_pcie_rp *pp = &pci->pp; in visconti_add_pcie_port()
283 pp->irq = platform_get_irq_byname(pdev, "intr"); in visconti_add_pcie_port()
284 if (pp->irq < 0) in visconti_add_pcie_port()
285 return pp->irq; in visconti_add_pcie_port()
287 pp->ops = &visconti_pcie_host_ops; in visconti_add_pcie_port()
294 struct device *dev = &pdev->dev; in visconti_pcie_probe()
295 struct visconti_pcie *pcie; in visconti_pcie_probe() local
299 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in visconti_pcie_probe()
300 if (!pcie) in visconti_pcie_probe()
301 return -ENOMEM; in visconti_pcie_probe()
303 pci = &pcie->pci; in visconti_pcie_probe()
304 pci->dev = dev; in visconti_pcie_probe()
305 pci->ops = &dw_pcie_ops; in visconti_pcie_probe()
307 ret = visconti_get_resources(pdev, pcie); in visconti_pcie_probe()
311 platform_set_drvdata(pdev, pcie); in visconti_pcie_probe()
313 return visconti_add_pcie_port(pcie, pdev); in visconti_pcie_probe()
317 { .compatible = "toshiba,visconti-pcie" },
324 .name = "visconti-pcie",