Lines Matching +full:pcie +full:- +full:apq8084
1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
28 #include <linux/phy/pcie.h>
37 #include "pcie-designware.h"
38 #include "pcie-qcom-common.h"
244 int (*get_resources)(struct qcom_pcie *pcie);
245 int (*init)(struct qcom_pcie *pcie);
246 int (*post_init)(struct qcom_pcie *pcie);
247 void (*host_post_init)(struct qcom_pcie *pcie);
248 void (*deinit)(struct qcom_pcie *pcie);
249 void (*ltssm_enable)(struct qcom_pcie *pcie);
250 int (*config_sid)(struct qcom_pcie *pcie);
254 * struct qcom_pcie_cfg - Per SoC config struct
255 * @ops: qcom PCIe ops structure
281 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
283 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
285 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
289 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
293 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
299 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_start_link() local
301 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { in qcom_pcie_start_link()
307 if (pcie->cfg->ops->ltssm_enable) in qcom_pcie_start_link()
308 pcie->cfg->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
315 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_clear_aspm_l0s() local
319 if (!pcie->cfg->no_l0s) in qcom_pcie_clear_aspm_l0s()
326 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
328 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
340 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
342 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
347 static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_base() argument
349 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_base()
351 if (pci->dbi_phys_addr) { in qcom_pcie_configure_dbi_base()
356 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_base()
358 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_base()
363 static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_atu_base() argument
365 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_atu_base()
367 if (pci->dbi_phys_addr) { in qcom_pcie_configure_dbi_atu_base()
373 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
375 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
378 if (pci->atu_phys_addr) { in qcom_pcie_configure_dbi_atu_base()
379 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
381 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
385 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); in qcom_pcie_configure_dbi_atu_base()
386 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_atu_base()
391 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_1_0_ltssm_enable() argument
396 val = readl(pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
398 writel(val, pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
401 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_1_0() argument
403 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_get_resources_2_1_0()
404 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_1_0()
405 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_1_0()
406 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); in qcom_pcie_get_resources_2_1_0()
409 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_1_0()
410 res->supplies[1].supply = "vdda_phy"; in qcom_pcie_get_resources_2_1_0()
411 res->supplies[2].supply = "vdda_refclk"; in qcom_pcie_get_resources_2_1_0()
412 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_1_0()
413 res->supplies); in qcom_pcie_get_resources_2_1_0()
417 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_1_0()
418 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_1_0()
420 return res->num_clks; in qcom_pcie_get_resources_2_1_0()
423 res->resets[0].id = "pci"; in qcom_pcie_get_resources_2_1_0()
424 res->resets[1].id = "axi"; in qcom_pcie_get_resources_2_1_0()
425 res->resets[2].id = "ahb"; in qcom_pcie_get_resources_2_1_0()
426 res->resets[3].id = "por"; in qcom_pcie_get_resources_2_1_0()
427 res->resets[4].id = "phy"; in qcom_pcie_get_resources_2_1_0()
428 res->resets[5].id = "ext"; in qcom_pcie_get_resources_2_1_0()
431 res->num_resets = is_apq ? 5 : 6; in qcom_pcie_get_resources_2_1_0()
432 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_1_0()
439 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_1_0() argument
441 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_deinit_2_1_0()
443 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_1_0()
444 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_1_0()
446 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
448 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_1_0()
451 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_1_0() argument
453 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_init_2_1_0()
454 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_1_0()
455 struct device *dev = pci->dev; in qcom_pcie_init_2_1_0()
458 /* reset the PCIe interface as uboot can leave it undefined state */ in qcom_pcie_init_2_1_0()
459 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
465 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
471 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
474 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
481 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_1_0() argument
483 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_post_init_2_1_0()
484 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_1_0()
485 struct device *dev = pci->dev; in qcom_pcie_post_init_2_1_0()
486 struct device_node *node = dev->of_node; in qcom_pcie_post_init_2_1_0()
490 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_1_0()
491 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
493 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
495 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_post_init_2_1_0()
499 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || in qcom_pcie_post_init_2_1_0()
500 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { in qcom_pcie_post_init_2_1_0()
504 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
507 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
508 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
511 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { in qcom_pcie_post_init_2_1_0()
513 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
516 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
520 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
522 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) in qcom_pcie_post_init_2_1_0()
525 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
532 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_post_init_2_1_0()
534 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_post_init_2_1_0()
536 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_1_0()
541 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_1_0_0() argument
543 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_get_resources_1_0_0()
544 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_1_0_0()
545 struct device *dev = pci->dev; in qcom_pcie_get_resources_1_0_0()
547 res->vdda = devm_regulator_get(dev, "vdda"); in qcom_pcie_get_resources_1_0_0()
548 if (IS_ERR(res->vdda)) in qcom_pcie_get_resources_1_0_0()
549 return PTR_ERR(res->vdda); in qcom_pcie_get_resources_1_0_0()
551 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_1_0_0()
552 if (res->num_clks < 0) { in qcom_pcie_get_resources_1_0_0()
554 return res->num_clks; in qcom_pcie_get_resources_1_0_0()
557 res->core = devm_reset_control_get_exclusive(dev, "core"); in qcom_pcie_get_resources_1_0_0()
558 return PTR_ERR_OR_ZERO(res->core); in qcom_pcie_get_resources_1_0_0()
561 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_1_0_0() argument
563 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_deinit_1_0_0()
565 reset_control_assert(res->core); in qcom_pcie_deinit_1_0_0()
566 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_1_0_0()
567 regulator_disable(res->vdda); in qcom_pcie_deinit_1_0_0()
570 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_init_1_0_0() argument
572 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_init_1_0_0()
573 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_1_0_0()
574 struct device *dev = pci->dev; in qcom_pcie_init_1_0_0()
577 ret = reset_control_deassert(res->core); in qcom_pcie_init_1_0_0()
583 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_1_0_0()
589 ret = regulator_enable(res->vdda); in qcom_pcie_init_1_0_0()
598 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_1_0_0()
600 reset_control_assert(res->core); in qcom_pcie_init_1_0_0()
605 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_1_0_0() argument
607 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_1_0_0()
610 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
613 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
616 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_1_0_0()
621 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_3_2_ltssm_enable() argument
626 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
628 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
631 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_2() argument
633 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_get_resources_2_3_2()
634 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_2()
635 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_2()
638 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_3_2()
639 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_3_2()
640 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_3_2()
641 res->supplies); in qcom_pcie_get_resources_2_3_2()
645 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_3_2()
646 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_3_2()
648 return res->num_clks; in qcom_pcie_get_resources_2_3_2()
654 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_2() argument
656 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_deinit_2_3_2()
658 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_3_2()
659 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_3_2()
662 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_2() argument
664 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_init_2_3_2()
665 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_2()
666 struct device *dev = pci->dev; in qcom_pcie_init_2_3_2()
669 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
675 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_3_2()
678 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
685 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_2() argument
689 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_3_2()
690 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
692 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
694 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_2_3_2()
697 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
699 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
701 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
703 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
705 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
707 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
709 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_3_2()
714 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_4_0() argument
716 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_get_resources_2_4_0()
717 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_4_0()
718 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_4_0()
719 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); in qcom_pcie_get_resources_2_4_0()
722 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_4_0()
723 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_4_0()
725 return res->num_clks; in qcom_pcie_get_resources_2_4_0()
728 res->resets[0].id = "axi_m"; in qcom_pcie_get_resources_2_4_0()
729 res->resets[1].id = "axi_s"; in qcom_pcie_get_resources_2_4_0()
730 res->resets[2].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_4_0()
731 res->resets[3].id = "pipe_sticky"; in qcom_pcie_get_resources_2_4_0()
732 res->resets[4].id = "pwr"; in qcom_pcie_get_resources_2_4_0()
733 res->resets[5].id = "ahb"; in qcom_pcie_get_resources_2_4_0()
734 res->resets[6].id = "pipe"; in qcom_pcie_get_resources_2_4_0()
735 res->resets[7].id = "axi_m_vmid"; in qcom_pcie_get_resources_2_4_0()
736 res->resets[8].id = "axi_s_xpu"; in qcom_pcie_get_resources_2_4_0()
737 res->resets[9].id = "parf"; in qcom_pcie_get_resources_2_4_0()
738 res->resets[10].id = "phy"; in qcom_pcie_get_resources_2_4_0()
739 res->resets[11].id = "phy_ahb"; in qcom_pcie_get_resources_2_4_0()
741 res->num_resets = is_ipq ? 12 : 6; in qcom_pcie_get_resources_2_4_0()
743 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_4_0()
750 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_4_0() argument
752 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_deinit_2_4_0()
754 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_4_0()
755 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_4_0()
758 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_4_0() argument
760 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_init_2_4_0()
761 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_4_0()
762 struct device *dev = pci->dev; in qcom_pcie_init_2_4_0()
765 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
773 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
781 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_4_0()
783 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
790 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_3() argument
792 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_get_resources_2_3_3()
793 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_3()
794 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_3()
797 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_3_3()
798 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_3_3()
800 return res->num_clks; in qcom_pcie_get_resources_2_3_3()
803 res->rst[0].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
804 res->rst[1].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
805 res->rst[2].id = "pipe"; in qcom_pcie_get_resources_2_3_3()
806 res->rst[3].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_3_3()
807 res->rst[4].id = "sticky"; in qcom_pcie_get_resources_2_3_3()
808 res->rst[5].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
809 res->rst[6].id = "sleep"; in qcom_pcie_get_resources_2_3_3()
811 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_get_resources_2_3_3()
818 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_3() argument
820 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_deinit_2_3_3()
822 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_3_3()
825 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_3() argument
827 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_init_2_3_3()
828 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_3()
829 struct device *dev = pci->dev; in qcom_pcie_init_2_3_3()
832 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
840 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
852 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_3_3()
865 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
870 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_3() argument
872 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_3_3()
876 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
878 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
880 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_3_3()
885 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
886 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
888 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); in qcom_pcie_post_init_2_3_3()
892 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_3_3()
894 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
896 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
898 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_3_3()
906 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_7_0() argument
908 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_get_resources_2_7_0()
909 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_7_0()
910 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_7_0()
913 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_7_0()
914 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_7_0()
915 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_7_0()
917 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_7_0()
918 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_7_0()
919 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_7_0()
920 res->supplies); in qcom_pcie_get_resources_2_7_0()
924 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_7_0()
925 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_7_0()
927 return res->num_clks; in qcom_pcie_get_resources_2_7_0()
933 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_7_0() argument
935 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_init_2_7_0()
936 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_7_0()
937 struct device *dev = pci->dev; in qcom_pcie_init_2_7_0()
941 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
947 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
951 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_7_0()
959 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_7_0()
968 /* configure PCIe to RC mode */ in qcom_pcie_init_2_7_0()
969 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
971 /* enable PCIe clocks and resets */ in qcom_pcie_init_2_7_0()
972 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
974 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
976 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_init_2_7_0()
979 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
981 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
983 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
985 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
988 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
990 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
992 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
994 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
998 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
1000 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
1005 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_7_0() argument
1007 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; in qcom_pcie_post_init_2_7_0()
1009 if (pcie_cfg->override_no_snoop) in qcom_pcie_post_init_2_7_0()
1011 pcie->parf + PARF_NO_SNOOP_OVERIDE); in qcom_pcie_post_init_2_7_0()
1013 qcom_pcie_clear_aspm_l0s(pcie->pci); in qcom_pcie_post_init_2_7_0()
1014 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_7_0()
1031 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_host_post_init_2_7_0() argument
1033 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_host_post_init_2_7_0()
1035 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL); in qcom_pcie_host_post_init_2_7_0()
1038 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_7_0() argument
1040 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_deinit_2_7_0()
1042 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_7_0()
1044 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_7_0()
1047 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) in qcom_pcie_config_sid_1_9_0() argument
1056 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
1057 struct device *dev = pcie->pci->dev; in qcom_pcie_config_sid_1_9_0()
1063 of_get_property(dev->of_node, "iommu-map", &size); in qcom_pcie_config_sid_1_9_0()
1068 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1070 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1074 return -ENOMEM; in qcom_pcie_config_sid_1_9_0()
1076 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, in qcom_pcie_config_sid_1_9_0()
1086 /* Extract the SMMU SID base from the first entry of iommu-map */ in qcom_pcie_config_sid_1_9_0()
1114 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; in qcom_pcie_config_sid_1_9_0()
1123 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_9_0() argument
1125 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_get_resources_2_9_0()
1126 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_9_0()
1127 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_9_0()
1129 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_9_0()
1130 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_9_0()
1132 return res->num_clks; in qcom_pcie_get_resources_2_9_0()
1135 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_9_0()
1136 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_9_0()
1137 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_9_0()
1142 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_9_0() argument
1144 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_deinit_2_9_0()
1146 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_9_0()
1149 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_9_0() argument
1151 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_init_2_9_0()
1152 struct device *dev = pcie->pci->dev; in qcom_pcie_init_2_9_0()
1155 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_9_0()
1167 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_9_0()
1175 return clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_9_0()
1178 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_9_0() argument
1180 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_9_0()
1185 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1187 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1189 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_9_0()
1191 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1193 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1196 pci->dbi_base + GEN3_RELATED_OFF); in qcom_pcie_post_init_2_9_0()
1201 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1203 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1207 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_9_0()
1209 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1211 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1213 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_9_0()
1219 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1227 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1235 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_init() local
1238 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1240 ret = pcie->cfg->ops->init(pcie); in qcom_pcie_host_init()
1244 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_host_init()
1248 ret = phy_power_on(pcie->phy); in qcom_pcie_host_init()
1252 if (pcie->cfg->ops->post_init) { in qcom_pcie_host_init()
1253 ret = pcie->cfg->ops->post_init(pcie); in qcom_pcie_host_init()
1258 qcom_ep_reset_deassert(pcie); in qcom_pcie_host_init()
1260 if (pcie->cfg->ops->config_sid) { in qcom_pcie_host_init()
1261 ret = pcie->cfg->ops->config_sid(pcie); in qcom_pcie_host_init()
1269 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1271 phy_power_off(pcie->phy); in qcom_pcie_host_init()
1273 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_init()
1281 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_deinit() local
1283 qcom_ep_reset_assert(pcie); in qcom_pcie_host_deinit()
1284 phy_power_off(pcie->phy); in qcom_pcie_host_deinit()
1285 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_deinit()
1291 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_post_init() local
1293 if (pcie->cfg->ops->host_post_init) in qcom_pcie_host_post_init()
1294 pcie->cfg->ops->host_post_init(pcie); in qcom_pcie_host_post_init()
1434 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) in qcom_pcie_icc_init() argument
1436 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_init()
1439 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); in qcom_pcie_icc_init()
1440 if (IS_ERR(pcie->icc_mem)) in qcom_pcie_icc_init()
1441 return PTR_ERR(pcie->icc_mem); in qcom_pcie_icc_init()
1443 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); in qcom_pcie_icc_init()
1444 if (IS_ERR(pcie->icc_cpu)) in qcom_pcie_icc_init()
1445 return PTR_ERR(pcie->icc_cpu); in qcom_pcie_icc_init()
1450 * Set an initial peak bandwidth corresponding to single-lane Gen 1 in qcom_pcie_icc_init()
1451 * for the pcie-mem path. in qcom_pcie_icc_init()
1453 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); in qcom_pcie_icc_init()
1455 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_init()
1461 * Since the CPU-PCIe path is only used for activities like register in qcom_pcie_icc_init()
1466 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); in qcom_pcie_icc_init()
1468 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", in qcom_pcie_icc_init()
1470 icc_set_bw(pcie->icc_mem, 0, 0); in qcom_pcie_icc_init()
1477 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) in qcom_pcie_icc_opp_update() argument
1480 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_opp_update()
1486 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_icc_opp_update()
1495 if (pcie->icc_mem) { in qcom_pcie_icc_opp_update()
1496 ret = icc_set_bw(pcie->icc_mem, 0, in qcom_pcie_icc_opp_update()
1499 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_opp_update()
1502 } else if (pcie->use_pm_opp) { in qcom_pcie_icc_opp_update()
1508 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, in qcom_pcie_icc_opp_update()
1511 ret = dev_pm_opp_set_opp(pci->dev, opp); in qcom_pcie_icc_opp_update()
1513 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", in qcom_pcie_icc_opp_update()
1522 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); in qcom_pcie_link_transition_count() local
1525 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); in qcom_pcie_link_transition_count()
1528 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); in qcom_pcie_link_transition_count()
1531 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); in qcom_pcie_link_transition_count()
1534 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); in qcom_pcie_link_transition_count()
1537 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); in qcom_pcie_link_transition_count()
1542 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) in qcom_pcie_init_debugfs() argument
1544 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_debugfs()
1545 struct device *dev = pci->dev; in qcom_pcie_init_debugfs()
1548 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in qcom_pcie_init_debugfs()
1552 pcie->debugfs = debugfs_create_dir(name, NULL); in qcom_pcie_init_debugfs()
1553 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, in qcom_pcie_init_debugfs()
1559 struct qcom_pcie *pcie = data; in qcom_pcie_global_irq_thread() local
1560 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_global_irq_thread()
1561 struct device *dev = pcie->pci->dev; in qcom_pcie_global_irq_thread()
1562 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); in qcom_pcie_global_irq_thread()
1564 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); in qcom_pcie_global_irq_thread()
1570 pci_rescan_bus(pp->bridge->bus); in qcom_pcie_global_irq_thread()
1573 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_global_irq_thread()
1586 struct device *dev = &pdev->dev; in qcom_pcie_probe()
1588 struct qcom_pcie *pcie; in qcom_pcie_probe() local
1596 if (!pcie_cfg || !pcie_cfg->ops) { in qcom_pcie_probe()
1598 return -EINVAL; in qcom_pcie_probe()
1601 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in qcom_pcie_probe()
1602 if (!pcie) in qcom_pcie_probe()
1603 return -ENOMEM; in qcom_pcie_probe()
1607 return -ENOMEM; in qcom_pcie_probe()
1614 pci->dev = dev; in qcom_pcie_probe()
1615 pci->ops = &dw_pcie_ops; in qcom_pcie_probe()
1616 pp = &pci->pp; in qcom_pcie_probe()
1618 pcie->pci = pci; in qcom_pcie_probe()
1620 pcie->cfg = pcie_cfg; in qcom_pcie_probe()
1622 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); in qcom_pcie_probe()
1623 if (IS_ERR(pcie->reset)) { in qcom_pcie_probe()
1624 ret = PTR_ERR(pcie->reset); in qcom_pcie_probe()
1628 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1629 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1630 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1634 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); in qcom_pcie_probe()
1635 if (IS_ERR(pcie->elbi)) { in qcom_pcie_probe()
1636 ret = PTR_ERR(pcie->elbi); in qcom_pcie_probe()
1643 pcie->mhi = devm_ioremap_resource(dev, res); in qcom_pcie_probe()
1644 if (IS_ERR(pcie->mhi)) { in qcom_pcie_probe()
1645 ret = PTR_ERR(pcie->mhi); in qcom_pcie_probe()
1650 pcie->phy = devm_phy_optional_get(dev, "pciephy"); in qcom_pcie_probe()
1651 if (IS_ERR(pcie->phy)) { in qcom_pcie_probe()
1652 ret = PTR_ERR(pcie->phy); in qcom_pcie_probe()
1658 if (ret && ret != -ENODEV) { in qcom_pcie_probe()
1664 * Before the PCIe link is initialized, vote for highest OPP in the OPP in qcom_pcie_probe()
1673 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1682 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1688 pcie->use_pm_opp = true; in qcom_pcie_probe()
1691 ret = qcom_pcie_icc_init(pcie); in qcom_pcie_probe()
1696 ret = pcie->cfg->ops->get_resources(pcie); in qcom_pcie_probe()
1700 pp->ops = &qcom_pcie_dw_ops; in qcom_pcie_probe()
1702 ret = phy_init(pcie->phy); in qcom_pcie_probe()
1706 platform_set_drvdata(pdev, pcie); in qcom_pcie_probe()
1710 pp->use_linkup_irq = true; in qcom_pcie_probe()
1719 pci_domain_nr(pp->bridge->bus)); in qcom_pcie_probe()
1721 ret = -ENOMEM; in qcom_pcie_probe()
1726 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in qcom_pcie_probe()
1728 IRQF_ONESHOT, name, pcie); in qcom_pcie_probe()
1730 dev_err_probe(&pdev->dev, ret, in qcom_pcie_probe()
1736 pcie->parf + PARF_INT_ALL_MASK); in qcom_pcie_probe()
1739 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_probe()
1741 if (pcie->mhi) in qcom_pcie_probe()
1742 qcom_pcie_init_debugfs(pcie); in qcom_pcie_probe()
1749 phy_exit(pcie->phy); in qcom_pcie_probe()
1759 struct qcom_pcie *pcie = dev_get_drvdata(dev); in qcom_pcie_suspend_noirq() local
1766 if (pcie->icc_mem) { in qcom_pcie_suspend_noirq()
1767 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); in qcom_pcie_suspend_noirq()
1770 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_suspend_noirq()
1777 * Turn OFF the resources only for controllers without active PCIe in qcom_pcie_suspend_noirq()
1781 * Turning OFF the resources for controllers with active PCIe devices in qcom_pcie_suspend_noirq()
1783 * as kernel tries to access the PCIe devices config space for masking in qcom_pcie_suspend_noirq()
1791 if (!dw_pcie_link_up(pcie->pci)) { in qcom_pcie_suspend_noirq()
1792 qcom_pcie_host_deinit(&pcie->pci->pp); in qcom_pcie_suspend_noirq()
1793 pcie->suspended = true; in qcom_pcie_suspend_noirq()
1797 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. in qcom_pcie_suspend_noirq()
1799 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC in qcom_pcie_suspend_noirq()
1803 ret = icc_disable(pcie->icc_cpu); in qcom_pcie_suspend_noirq()
1805 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_suspend_noirq()
1807 if (pcie->use_pm_opp) in qcom_pcie_suspend_noirq()
1808 dev_pm_opp_set_opp(pcie->pci->dev, NULL); in qcom_pcie_suspend_noirq()
1815 struct qcom_pcie *pcie = dev_get_drvdata(dev); in qcom_pcie_resume_noirq() local
1819 ret = icc_enable(pcie->icc_cpu); in qcom_pcie_resume_noirq()
1821 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_resume_noirq()
1826 if (pcie->suspended) { in qcom_pcie_resume_noirq()
1827 ret = qcom_pcie_host_init(&pcie->pci->pp); in qcom_pcie_resume_noirq()
1831 pcie->suspended = false; in qcom_pcie_resume_noirq()
1834 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_resume_noirq()
1840 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1841 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1842 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1843 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1844 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1845 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1846 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1847 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1848 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
1849 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1850 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1851 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
1852 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
1853 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1854 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1855 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
1856 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1857 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1858 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1859 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1860 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1861 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1862 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1863 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1864 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
1870 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in qcom_fixup_class()
1887 .name = "qcom-pcie",