Lines Matching +full:pci +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-[email protected]>
9 * Implementation based on pci-exynos.c and pcie-designware.c
24 #include <linux/phy/phy.h>
30 #include "../../pci.h"
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
122 struct dw_pcie *pci; member
123 /* PCI Device ID */
130 struct phy **phy; member
144 return readl(ks_pcie->va_app_base + offset); in ks_pcie_app_readl()
150 writel(val, ks_pcie->va_app_base + offset); in ks_pcie_app_writel()
157 u32 irq = data->hwirq; in ks_pcie_msi_irq_ack()
158 struct dw_pcie *pci; in ks_pcie_msi_irq_ack() local
162 pci = to_dw_pcie_from_pp(pp); in ks_pcie_msi_irq_ack()
163 ks_pcie = to_keystone_pcie(pci); in ks_pcie_msi_irq_ack()
177 struct dw_pcie *pci; in ks_pcie_compose_msi_msg() local
180 pci = to_dw_pcie_from_pp(pp); in ks_pcie_compose_msi_msg()
181 ks_pcie = to_keystone_pcie(pci); in ks_pcie_compose_msi_msg()
183 msi_target = ks_pcie->app.start + MSI_IRQ; in ks_pcie_compose_msi_msg()
184 msg->address_lo = lower_32_bits(msi_target); in ks_pcie_compose_msi_msg()
185 msg->address_hi = upper_32_bits(msi_target); in ks_pcie_compose_msi_msg()
186 msg->data = data->hwirq; in ks_pcie_compose_msi_msg()
188 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", in ks_pcie_compose_msi_msg()
189 (int)data->hwirq, msg->address_hi, msg->address_lo); in ks_pcie_compose_msi_msg()
196 u32 irq = data->hwirq; in ks_pcie_msi_mask()
197 struct dw_pcie *pci; in ks_pcie_msi_mask() local
202 raw_spin_lock_irqsave(&pp->lock, flags); in ks_pcie_msi_mask()
204 pci = to_dw_pcie_from_pp(pp); in ks_pcie_msi_mask()
205 ks_pcie = to_keystone_pcie(pci); in ks_pcie_msi_mask()
213 raw_spin_unlock_irqrestore(&pp->lock, flags); in ks_pcie_msi_mask()
220 u32 irq = data->hwirq; in ks_pcie_msi_unmask()
221 struct dw_pcie *pci; in ks_pcie_msi_unmask() local
226 raw_spin_lock_irqsave(&pp->lock, flags); in ks_pcie_msi_unmask()
228 pci = to_dw_pcie_from_pp(pp); in ks_pcie_msi_unmask()
229 ks_pcie = to_keystone_pcie(pci); in ks_pcie_msi_unmask()
237 raw_spin_unlock_irqrestore(&pp->lock, flags); in ks_pcie_msi_unmask()
241 .name = "KEYSTONE-PCI-MSI",
249 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
270 * ks_pcie_clear_dbi_mode() - Disable DBI mode
292 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in ks_pcie_msi_host_init() local
293 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_msi_host_init()
299 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); in ks_pcie_msi_host_init()
300 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); in ks_pcie_msi_host_init()
308 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); in ks_pcie_msi_host_init()
310 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; in ks_pcie_msi_host_init()
317 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_handle_intx_irq() local
318 struct device *dev = pci->dev; in ks_pcie_handle_intx_irq()
325 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); in ks_pcie_handle_intx_irq()
340 struct device *dev = ks_pcie->pci->dev; in ks_pcie_handle_error_irq()
358 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) in ks_pcie_handle_error_irq()
361 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) in ks_pcie_handle_error_irq()
382 .name = "Keystone-PCI-INTX-IRQ",
393 irq_set_chip_data(irq, d->host_data); in ks_pcie_init_intx_irq_map()
406 u32 num_viewport = ks_pcie->num_viewport; in ks_pcie_setup_rc_app_regs()
407 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_setup_rc_app_regs() local
408 struct dw_pcie_rp *pp = &pci->pp; in ks_pcie_setup_rc_app_regs()
414 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); in ks_pcie_setup_rc_app_regs()
416 return -ENODEV; in ks_pcie_setup_rc_app_regs()
418 mem = entry->res; in ks_pcie_setup_rc_app_regs()
419 start = mem->start; in ks_pcie_setup_rc_app_regs()
420 end = mem->end; in ks_pcie_setup_rc_app_regs()
424 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); in ks_pcie_setup_rc_app_regs()
425 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); in ks_pcie_setup_rc_app_regs()
428 if (ks_pcie->is_am6) in ks_pcie_setup_rc_app_regs()
434 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ in ks_pcie_setup_rc_app_regs()
453 struct dw_pcie_rp *pp = bus->sysdata; in ks_pcie_other_map_bus()
454 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in ks_pcie_other_map_bus() local
455 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_other_map_bus()
461 * SError upon PCI configuration transactions issued when the link in ks_pcie_other_map_bus()
466 if (!dw_pcie_link_up(pci)) in ks_pcie_other_map_bus()
469 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | in ks_pcie_other_map_bus()
471 if (!pci_is_root_bus(bus->parent)) in ks_pcie_other_map_bus()
475 return pp->va_cfg0_base + where; in ks_pcie_other_map_bus()
491 * ks_pcie_link_up() - Check if link up
492 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host
495 static int ks_pcie_link_up(struct dw_pcie *pci) in ks_pcie_link_up() argument
499 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); in ks_pcie_link_up()
504 static void ks_pcie_stop_link(struct dw_pcie *pci) in ks_pcie_stop_link() argument
506 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_stop_link()
515 static int ks_pcie_start_link(struct dw_pcie *pci) in ks_pcie_start_link() argument
517 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_start_link()
529 struct pci_bus *bus = dev->bus; in ks_pcie_quirk()
557 bridge = bus->self; in ks_pcie_quirk()
558 bus = bus->parent; in ks_pcie_quirk()
565 * Keystone PCI controller has a h/w limitation of in ks_pcie_quirk()
572 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); in ks_pcie_quirk()
578 * Memory transactions fail with PCI controller in AM654 PG1.0 in ks_pcie_quirk()
584 if (!bridge_dev || !bridge_dev->parent) in ks_pcie_quirk()
587 ks_pcie = dev_get_drvdata(bridge_dev->parent); in ks_pcie_quirk()
598 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); in ks_pcie_quirk()
607 unsigned int irq = desc->irq_data.hwirq; in ks_pcie_msi_irq_handler()
609 u32 offset = irq - ks_pcie->msi_host_irq; in ks_pcie_msi_irq_handler()
610 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_msi_irq_handler() local
611 struct dw_pcie_rp *pp = &pci->pp; in ks_pcie_msi_irq_handler()
612 struct device *dev = pci->dev; in ks_pcie_msi_irq_handler()
627 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit in ks_pcie_msi_irq_handler()
636 generic_handle_domain_irq(pp->irq_domain, vector); in ks_pcie_msi_irq_handler()
643 * ks_pcie_intx_irq_handler() - Handle INTX interrupt
653 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_intx_irq_handler() local
654 struct device *dev = pci->dev; in ks_pcie_intx_irq_handler()
655 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; in ks_pcie_intx_irq_handler()
672 struct device *dev = ks_pcie->pci->dev; in ks_pcie_config_msi_irq()
673 struct device_node *np = ks_pcie->np; in ks_pcie_config_msi_irq()
681 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); in ks_pcie_config_msi_irq()
683 if (ks_pcie->is_am6) in ks_pcie_config_msi_irq()
685 dev_warn(dev, "msi-interrupt-controller node is absent\n"); in ks_pcie_config_msi_irq()
686 return -EINVAL; in ks_pcie_config_msi_irq()
691 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); in ks_pcie_config_msi_irq()
692 ret = -EINVAL; in ks_pcie_config_msi_irq()
699 ret = -EINVAL; in ks_pcie_config_msi_irq()
703 if (!ks_pcie->msi_host_irq) { in ks_pcie_config_msi_irq()
706 ret = -EINVAL; in ks_pcie_config_msi_irq()
709 ks_pcie->msi_host_irq = irq_data->hwirq; in ks_pcie_config_msi_irq()
726 struct device *dev = ks_pcie->pci->dev; in ks_pcie_config_intx_irq()
728 struct device_node *np = ks_pcie->np; in ks_pcie_config_intx_irq()
732 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); in ks_pcie_config_intx_irq()
735 * Since INTX interrupts are modeled as edge-interrupts in in ks_pcie_config_intx_irq()
738 if (ks_pcie->is_am6) in ks_pcie_config_intx_irq()
740 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); in ks_pcie_config_intx_irq()
741 return -EINVAL; in ks_pcie_config_intx_irq()
746 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); in ks_pcie_config_intx_irq()
747 ret = -EINVAL; in ks_pcie_config_intx_irq()
754 ret = -EINVAL; in ks_pcie_config_intx_irq()
757 ks_pcie->intx_host_irqs[i] = irq; in ks_pcie_config_intx_irq()
768 ret = -EINVAL; in ks_pcie_config_intx_irq()
771 ks_pcie->intx_irq_domain = intx_irq_domain; in ks_pcie_config_intx_irq()
783 * When a PCI device does not exist during config cycles, keystone host
795 regs->uregs[reg] = -1; in ks_pcie_fault()
796 regs->ARM_pc += 4; in ks_pcie_fault()
808 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_init_id() local
809 struct device *dev = pci->dev; in ks_pcie_init_id()
810 struct device_node *np = dev->of_node; in ks_pcie_init_id()
814 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); in ks_pcie_init_id()
819 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); in ks_pcie_init_id()
827 dw_pcie_dbi_ro_wr_en(pci); in ks_pcie_init_id()
828 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); in ks_pcie_init_id()
829 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); in ks_pcie_init_id()
830 dw_pcie_dbi_ro_wr_dis(pci); in ks_pcie_init_id()
837 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in ks_pcie_host_init() local
838 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_host_init()
841 pp->bridge->ops = &ks_pcie_ops; in ks_pcie_host_init()
842 if (!ks_pcie->is_am6) in ks_pcie_host_init()
843 pp->bridge->child_ops = &ks_child_pcie_ops; in ks_pcie_host_init()
853 ks_pcie_stop_link(pci); in ks_pcie_host_init()
859 pci->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
893 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, in ks_pcie_am654_write_dbi2() argument
896 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_am654_write_dbi2()
912 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ks_pcie_am654_ep_init() local
915 ep->page_size = AM654_WIN_SIZE; in ks_pcie_am654_ep_init()
917 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); in ks_pcie_am654_ep_init()
918 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); in ks_pcie_am654_ep_init()
923 struct dw_pcie *pci = ks_pcie->pci; in ks_pcie_am654_raise_intx_irq() local
926 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); in ks_pcie_am654_raise_intx_irq()
942 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ks_pcie_am654_raise_irq() local
943 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); in ks_pcie_am654_raise_irq()
956 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in ks_pcie_am654_raise_irq()
957 return -EINVAL; in ks_pcie_am654_raise_irq()
990 int num_lanes = ks_pcie->num_lanes; in ks_pcie_disable_phy()
992 while (num_lanes--) { in ks_pcie_disable_phy()
993 phy_power_off(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
994 phy_exit(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
1002 int num_lanes = ks_pcie->num_lanes; in ks_pcie_enable_phy()
1005 ret = phy_reset(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1009 ret = phy_init(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1013 ret = phy_power_on(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1015 phy_exit(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1023 while (--i >= 0) { in ks_pcie_enable_phy()
1024 phy_power_off(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1025 phy_exit(ks_pcie->phy[i]); in ks_pcie_enable_phy()
1033 struct device_node *np = dev->of_node; in ks_pcie_set_mode()
1041 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); in ks_pcie_set_mode()
1046 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); in ks_pcie_set_mode()
1065 struct device_node *np = dev->of_node; in ks_pcie_am654_set_mode()
1073 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); in ks_pcie_am654_set_mode()
1078 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); in ks_pcie_am654_set_mode()
1093 return -EINVAL; in ks_pcie_am654_set_mode()
1125 .type = "pci",
1127 .compatible = "ti,keystone-pcie",
1131 .compatible = "ti,am654-pcie-rc",
1135 .compatible = "ti,am654-pcie-ep",
1144 struct device *dev = &pdev->dev; in ks_pcie_probe()
1145 struct device_node *np = dev->of_node; in ks_pcie_probe()
1148 struct dw_pcie *pci; in ks_pcie_probe() local
1155 struct phy **phy; in ks_pcie_probe() local
1165 return -EINVAL; in ks_pcie_probe()
1167 version = data->version; in ks_pcie_probe()
1168 host_ops = data->host_ops; in ks_pcie_probe()
1169 ep_ops = data->ep_ops; in ks_pcie_probe()
1170 mode = data->mode; in ks_pcie_probe()
1174 return -ENOMEM; in ks_pcie_probe()
1176 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); in ks_pcie_probe()
1177 if (!pci) in ks_pcie_probe()
1178 return -ENOMEM; in ks_pcie_probe()
1181 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); in ks_pcie_probe()
1182 if (IS_ERR(ks_pcie->va_app_base)) in ks_pcie_probe()
1183 return PTR_ERR(ks_pcie->va_app_base); in ks_pcie_probe()
1185 ks_pcie->app = *res; in ks_pcie_probe()
1192 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) in ks_pcie_probe()
1193 ks_pcie->is_am6 = true; in ks_pcie_probe()
1195 pci->dbi_base = base; in ks_pcie_probe()
1196 pci->dbi_base2 = base; in ks_pcie_probe()
1197 pci->dev = dev; in ks_pcie_probe()
1198 pci->ops = &ks_pcie_dw_pcie_ops; in ks_pcie_probe()
1199 pci->version = version; in ks_pcie_probe()
1206 "ks-pcie-error-irq", ks_pcie); in ks_pcie_probe()
1213 ret = of_property_read_u32(np, "num-lanes", &num_lanes); in ks_pcie_probe()
1217 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); in ks_pcie_probe()
1218 if (!phy) in ks_pcie_probe()
1219 return -ENOMEM; in ks_pcie_probe()
1223 return -ENOMEM; in ks_pcie_probe()
1226 snprintf(name, sizeof(name), "pcie-phy%d", i); in ks_pcie_probe()
1227 phy[i] = devm_phy_optional_get(dev, name); in ks_pcie_probe()
1228 if (IS_ERR(phy[i])) { in ks_pcie_probe()
1229 ret = PTR_ERR(phy[i]); in ks_pcie_probe()
1233 if (!phy[i]) in ks_pcie_probe()
1236 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); in ks_pcie_probe()
1238 ret = -EINVAL; in ks_pcie_probe()
1243 ks_pcie->np = np; in ks_pcie_probe()
1244 ks_pcie->pci = pci; in ks_pcie_probe()
1245 ks_pcie->link = link; in ks_pcie_probe()
1246 ks_pcie->num_lanes = num_lanes; in ks_pcie_probe()
1247 ks_pcie->phy = phy; in ks_pcie_probe()
1253 if (ret != -EPROBE_DEFER) in ks_pcie_probe()
1260 phy_pm_runtime_get_sync(ks_pcie->phy[i]); in ks_pcie_probe()
1266 phy_pm_runtime_put_sync(ks_pcie->phy[i]); in ks_pcie_probe()
1269 dev_err(dev, "failed to enable phy\n"); in ks_pcie_probe()
1281 if (dw_pcie_ver_is_ge(pci, 480A)) in ks_pcie_probe()
1291 ret = -ENODEV; in ks_pcie_probe()
1295 ret = of_property_read_u32(np, "num-viewport", &num_viewport); in ks_pcie_probe()
1297 dev_err(dev, "unable to read *num-viewport* property\n"); in ks_pcie_probe()
1303 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 in ks_pcie_probe()
1306 * mode is selected while enabling the PHY. So deassert PERST# in ks_pcie_probe()
1314 ks_pcie->num_viewport = num_viewport; in ks_pcie_probe()
1315 pci->pp.ops = host_ops; in ks_pcie_probe()
1316 ret = dw_pcie_host_init(&pci->pp); in ks_pcie_probe()
1322 ret = -ENODEV; in ks_pcie_probe()
1326 pci->ep.ops = ep_ops; in ks_pcie_probe()
1327 ret = dw_pcie_ep_init(&pci->ep); in ks_pcie_probe()
1331 ret = dw_pcie_ep_init_registers(&pci->ep); in ks_pcie_probe()
1337 pci_epc_init_notify(pci->ep.epc); in ks_pcie_probe()
1349 dw_pcie_ep_deinit(&pci->ep); in ks_pcie_probe()
1356 while (--i >= 0 && link[i]) in ks_pcie_probe()
1365 struct device_link **link = ks_pcie->link; in ks_pcie_remove()
1366 int num_lanes = ks_pcie->num_lanes; in ks_pcie_remove()
1367 struct device *dev = &pdev->dev; in ks_pcie_remove()
1372 while (num_lanes--) in ks_pcie_remove()
1380 .name = "keystone-pcie",