Lines Matching +full:imx7 +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
30 #include <linux/reset.h>
37 #include "pcie-designware.h"
75 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
110 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
170 /* PCIe Port Logic registers (memory-mapped) */
183 /* PHY registers (not memory-mapped) */
197 /* iMX7 PCIe PHY registers */
220 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
221 imx_pcie->drvdata->variant != IMX8MQ_EP && in imx_pcie_grp_offset()
222 imx_pcie->drvdata->variant != IMX8MM && in imx_pcie_grp_offset()
223 imx_pcie->drvdata->variant != IMX8MM_EP && in imx_pcie_grp_offset()
224 imx_pcie->drvdata->variant != IMX8MP && in imx_pcie_grp_offset()
225 imx_pcie->drvdata->variant != IMX8MP_EP); in imx_pcie_grp_offset()
226 return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx_pcie_grp_offset()
231 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
236 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
239 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
249 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_configure_type()
252 if (drvdata->mode == DW_PCIE_EP_TYPE) in imx_pcie_configure_type()
257 id = imx_pcie->controller_id; in imx_pcie_configure_type()
260 if (!drvdata->mode_mask[0]) in imx_pcie_configure_type()
264 if (!drvdata->mode_mask[id]) in imx_pcie_configure_type()
267 mask = drvdata->mode_mask[id]; in imx_pcie_configure_type()
268 val = mode << (ffs(mask) - 1); in imx_pcie_configure_type()
270 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); in imx_pcie_configure_type()
275 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_poll_ack()
291 return -ETIMEDOUT; in pcie_phy_poll_ack()
296 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_wait_ack()
316 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
319 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_read()
345 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_write()
370 /* wait for ack de-assertion */ in pcie_phy_write()
388 /* wait for ack de-assertion */ in pcie_phy_write()
401 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx8mq_pcie_init_phy()
410 if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) in imx8mq_pcie_init_phy()
411 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx8mq_pcie_init_phy()
421 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx_pcie_init_phy()
425 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx_pcie_init_phy()
428 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
430 imx_pcie->tx_deemph_gen1 << 0); in imx_pcie_init_phy()
431 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
433 imx_pcie->tx_deemph_gen2_3p5db << 6); in imx_pcie_init_phy()
434 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
436 imx_pcie->tx_deemph_gen2_6db << 12); in imx_pcie_init_phy()
437 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
439 imx_pcie->tx_swing_full << 18); in imx_pcie_init_phy()
440 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
442 imx_pcie->tx_swing_low << 25); in imx_pcie_init_phy()
448 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_init_phy()
457 struct device *dev = imx_pcie->pci->dev; in imx7d_pcie_wait_for_phy_pll_lock()
459 if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, in imx7d_pcie_wait_for_phy_pll_lock()
474 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) in imx_setup_phy_mpll()
477 for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) in imx_setup_phy_mpll()
478 if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0) in imx_setup_phy_mpll()
479 phy_rate = clk_get_rate(imx_pcie->clks[i].clk); in imx_setup_phy_mpll()
497 dev_err(imx_pcie->pci->dev, in imx_setup_phy_mpll()
499 return -EINVAL; in imx_setup_phy_mpll()
523 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) in imx_pcie_reset_phy()
550 * make it look like it read all-ones. in imx6q_pcie_abort_handler()
558 val = -1; in imx6q_pcie_abort_handler()
560 regs->uregs[reg] = val; in imx6q_pcie_abort_handler()
561 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
566 regs->uregs[reg] = -1; in imx6q_pcie_abort_handler()
567 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
581 if (dev->pm_domain) in imx_pcie_attach_pd()
584 imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); in imx_pcie_attach_pd()
585 if (IS_ERR(imx_pcie->pd_pcie)) in imx_pcie_attach_pd()
586 return PTR_ERR(imx_pcie->pd_pcie); in imx_pcie_attach_pd()
588 if (!imx_pcie->pd_pcie) in imx_pcie_attach_pd()
590 link = device_link_add(dev, imx_pcie->pd_pcie, in imx_pcie_attach_pd()
596 return -EINVAL; in imx_pcie_attach_pd()
599 imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); in imx_pcie_attach_pd()
600 if (IS_ERR(imx_pcie->pd_pcie_phy)) in imx_pcie_attach_pd()
601 return PTR_ERR(imx_pcie->pd_pcie_phy); in imx_pcie_attach_pd()
603 link = device_link_add(dev, imx_pcie->pd_pcie_phy, in imx_pcie_attach_pd()
609 return -EINVAL; in imx_pcie_attach_pd()
617 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_enable_ref_clk()
627 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_enable_ref_clk()
629 * The async reset input need ref clock to sync internally, in imx6q_pcie_enable_ref_clk()
630 * when the ref clock comes after reset, internal synced in imx6q_pcie_enable_ref_clk()
631 * reset time is too short, cannot meet the requirement. in imx6q_pcie_enable_ref_clk()
635 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_enable_ref_clk()
637 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_enable_ref_clk()
638 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_enable_ref_clk()
648 regmap_update_bits(imx_pcie->iomuxc_gpr, offset, in imx8mm_pcie_enable_ref_clk()
651 regmap_update_bits(imx_pcie->iomuxc_gpr, offset, in imx8mm_pcie_enable_ref_clk()
659 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx7d_pcie_enable_ref_clk()
667 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_clk_enable()
668 struct device *dev = pci->dev; in imx_pcie_clk_enable()
671 ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); in imx_pcie_clk_enable()
675 if (imx_pcie->drvdata->enable_ref_clk) { in imx_pcie_clk_enable()
676 ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); in imx_pcie_clk_enable()
688 clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); in imx_pcie_clk_enable()
695 if (imx_pcie->drvdata->enable_ref_clk) in imx_pcie_clk_disable()
696 imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); in imx_pcie_clk_disable()
697 clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); in imx_pcie_clk_disable()
703 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_core_reset()
706 /* Force PCIe PHY reset */ in imx6sx_pcie_core_reset()
707 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, in imx6sx_pcie_core_reset()
714 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, in imx6qp_pcie_core_reset()
727 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_core_reset()
728 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_core_reset()
735 struct dw_pcie *pci = imx_pcie->pci; in imx7d_pcie_core_reset()
736 struct device *dev = pci->dev; in imx7d_pcie_core_reset()
750 * The Duty-cycle Corrector calibration must be disabled. in imx7d_pcie_core_reset()
752 * 1. De-assert the G_RST signal by clearing in imx7d_pcie_core_reset()
754 * 2. De-assert DCC_FB_EN by writing data “0x29” to the register in imx7d_pcie_core_reset()
760 * 5. De-assert the CMN_RST signal by clearing register bit in imx7d_pcie_core_reset()
764 if (likely(imx_pcie->phy_base)) { in imx7d_pcie_core_reset()
765 /* De-assert DCC_FB_EN */ in imx7d_pcie_core_reset()
766 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); in imx7d_pcie_core_reset()
769 imx_pcie->phy_base + PCIE_PHY_CMN_REG24); in imx7d_pcie_core_reset()
771 writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); in imx7d_pcie_core_reset()
773 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); in imx7d_pcie_core_reset()
781 reset_control_assert(imx_pcie->pciephy_reset); in imx_pcie_assert_core_reset()
782 reset_control_assert(imx_pcie->apps_reset); in imx_pcie_assert_core_reset()
784 if (imx_pcie->drvdata->core_reset) in imx_pcie_assert_core_reset()
785 imx_pcie->drvdata->core_reset(imx_pcie, true); in imx_pcie_assert_core_reset()
787 /* Some boards don't have PCIe reset GPIO. */ in imx_pcie_assert_core_reset()
788 gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); in imx_pcie_assert_core_reset()
793 reset_control_deassert(imx_pcie->pciephy_reset); in imx_pcie_deassert_core_reset()
794 reset_control_deassert(imx_pcie->apps_reset); in imx_pcie_deassert_core_reset()
796 if (imx_pcie->drvdata->core_reset) in imx_pcie_deassert_core_reset()
797 imx_pcie->drvdata->core_reset(imx_pcie, false); in imx_pcie_deassert_core_reset()
799 /* Some boards don't have PCIe reset GPIO. */ in imx_pcie_deassert_core_reset()
800 if (imx_pcie->reset_gpiod) { in imx_pcie_deassert_core_reset()
802 gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0); in imx_pcie_deassert_core_reset()
812 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_wait_for_speed_change()
813 struct device *dev = pci->dev; in imx_pcie_wait_for_speed_change()
826 return -ETIMEDOUT; in imx_pcie_wait_for_speed_change()
832 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_ltssm_enable()
833 u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); in imx_pcie_ltssm_enable()
836 tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); in imx_pcie_ltssm_enable()
837 phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); in imx_pcie_ltssm_enable()
838 if (drvdata->ltssm_mask) in imx_pcie_ltssm_enable()
839 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, in imx_pcie_ltssm_enable()
840 drvdata->ltssm_mask); in imx_pcie_ltssm_enable()
842 reset_control_deassert(imx_pcie->apps_reset); in imx_pcie_ltssm_enable()
848 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_ltssm_disable()
850 phy_set_speed(imx_pcie->phy, 0); in imx_pcie_ltssm_disable()
851 if (drvdata->ltssm_mask) in imx_pcie_ltssm_disable()
852 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, in imx_pcie_ltssm_disable()
853 drvdata->ltssm_mask, 0); in imx_pcie_ltssm_disable()
855 reset_control_assert(imx_pcie->apps_reset); in imx_pcie_ltssm_disable()
861 struct device *dev = pci->dev; in imx_pcie_start_link()
885 if (pci->max_link_speed > 1) { in imx_pcie_start_link()
890 tmp |= pci->max_link_speed; in imx_pcie_start_link()
902 if (imx_pcie->drvdata->flags & in imx_pcie_start_link()
908 * occurs and we go Gen1 -> yep, Gen1. The difference in imx_pcie_start_link()
942 struct device *dev = pci->dev; in imx_pcie_stop_link()
950 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_add_lut()
951 struct device *dev = pci->dev; in imx_pcie_add_lut()
953 int free = -1; in imx_pcie_add_lut()
958 return -EINVAL; in imx_pcie_add_lut()
961 guard(mutex)(&imx_pcie->lock); in imx_pcie_add_lut()
969 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_add_lut()
971 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); in imx_pcie_add_lut()
979 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_add_lut()
990 return -ENOSPC; in imx_pcie_add_lut()
996 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); in imx_pcie_add_lut()
1000 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); in imx_pcie_add_lut()
1002 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); in imx_pcie_add_lut()
1012 guard(mutex)(&imx_pcie->lock); in imx_pcie_remove_lut()
1015 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1017 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_remove_lut()
1019 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1021 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1023 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1034 struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); in imx_pcie_enable_device()
1041 dev = imx_pcie->pci->dev; in imx_pcie_enable_device()
1044 err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", in imx_pcie_enable_device()
1054 err_i = -EINVAL; in imx_pcie_enable_device()
1058 err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", in imx_pcie_enable_device()
1065 * support it, so return -EINVAL. in imx_pcie_enable_device()
1066 * != 0 NULL msi-map does not exist, use built-in MSI in imx_pcie_enable_device()
1071 return -EINVAL; in imx_pcie_enable_device()
1073 of_node_put(target); /* Find streamID map entry for RID in msi-map */ in imx_pcie_enable_device()
1076 * msi-map iommu-map in imx_pcie_enable_device()
1090 * │ LUT │ 6-bit streamID │ │ in imx_pcie_enable_device()
1092 * └─────┘ 2-bit ctrl ID │ │ in imx_pcie_enable_device()
1104 dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); in imx_pcie_enable_device()
1105 return -EINVAL; in imx_pcie_enable_device()
1122 imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); in imx_pcie_disable_device()
1129 struct device *dev = pci->dev; in imx_pcie_host_init()
1133 if (imx_pcie->vpcie) { in imx_pcie_host_init()
1134 ret = regulator_enable(imx_pcie->vpcie); in imx_pcie_host_init()
1142 if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { in imx_pcie_host_init()
1143 pp->bridge->enable_device = imx_pcie_enable_device; in imx_pcie_host_init()
1144 pp->bridge->disable_device = imx_pcie_disable_device; in imx_pcie_host_init()
1149 if (imx_pcie->drvdata->init_phy) in imx_pcie_host_init()
1150 imx_pcie->drvdata->init_phy(imx_pcie); in imx_pcie_host_init()
1160 if (imx_pcie->phy) { in imx_pcie_host_init()
1161 ret = phy_init(imx_pcie->phy); in imx_pcie_host_init()
1167 ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, in imx_pcie_host_init()
1168 imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ? in imx_pcie_host_init()
1175 ret = phy_power_on(imx_pcie->phy); in imx_pcie_host_init()
1184 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); in imx_pcie_host_init()
1193 phy_power_off(imx_pcie->phy); in imx_pcie_host_init()
1195 phy_exit(imx_pcie->phy); in imx_pcie_host_init()
1199 if (imx_pcie->vpcie) in imx_pcie_host_init()
1200 regulator_disable(imx_pcie->vpcie); in imx_pcie_host_init()
1209 if (imx_pcie->phy) { in imx_pcie_host_exit()
1210 if (phy_power_off(imx_pcie->phy)) in imx_pcie_host_exit()
1211 dev_err(pci->dev, "unable to power off PHY\n"); in imx_pcie_host_exit()
1212 phy_exit(imx_pcie->phy); in imx_pcie_host_exit()
1216 if (imx_pcie->vpcie) in imx_pcie_host_exit()
1217 regulator_disable(imx_pcie->vpcie); in imx_pcie_host_exit()
1223 struct dw_pcie_rp *pp = &pcie->pp; in imx_pcie_cpu_addr_fixup()
1226 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) in imx_pcie_cpu_addr_fixup()
1229 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); in imx_pcie_cpu_addr_fixup()
1233 return cpu_addr - entry->offset; in imx_pcie_cpu_addr_fixup()
1246 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); in imx_pcie_pme_turn_off()
1247 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); in imx_pcie_pme_turn_off()
1291 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in imx_pcie_ep_raise_irq()
1292 return -EINVAL; in imx_pcie_ep_raise_irq()
1321 * BAR0 | Enable | 64-bit | 1 MB | Programmable Size
1322 * BAR1 | Disable | 32-bit | 64 KB | Fixed Size
1323 * (BAR1 should be disabled if BAR0 is 64-bit)
1324 * BAR2 | Enable | 32-bit | 1 MB | Programmable Size
1325 * BAR3 | Enable | 32-bit | 64 KB | Programmable Size
1326 * BAR4 | Enable | 32-bit | 1 MB | Programmable Size
1327 * BAR5 | Enable | 32-bit | 64 KB | Programmable Size
1341 return imx_pcie->drvdata->epc_features; in imx_pcie_ep_get_features()
1355 struct dw_pcie *pci = imx_pcie->pci; in imx_add_pcie_ep()
1356 struct dw_pcie_rp *pp = &pci->pp; in imx_add_pcie_ep()
1357 struct device *dev = pci->dev; in imx_add_pcie_ep()
1360 ep = &pci->ep; in imx_add_pcie_ep()
1361 ep->ops = &pcie_ep_ops; in imx_add_pcie_ep()
1366 ep->page_size = imx_pcie->drvdata->epc_features->align; in imx_add_pcie_ep()
1381 pci_epc_init_notify(ep->epc); in imx_add_pcie_ep()
1393 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_msi_save_restore()
1399 imx_pcie->msi_ctrl = val; in imx_pcie_msi_save_restore()
1402 val = imx_pcie->msi_ctrl; in imx_pcie_msi_save_restore()
1413 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx_pcie_suspend_noirq()
1424 imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); in imx_pcie_suspend_noirq()
1426 return dw_pcie_suspend_noirq(imx_pcie->pci); in imx_pcie_suspend_noirq()
1437 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx_pcie_resume_noirq()
1441 ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); in imx_pcie_resume_noirq()
1453 ret = dw_pcie_setup_rc(&imx_pcie->pci->pp); in imx_pcie_resume_noirq()
1457 ret = dw_pcie_resume_noirq(imx_pcie->pci); in imx_pcie_resume_noirq()
1473 struct device *dev = &pdev->dev; in imx_pcie_probe()
1478 struct device_node *node = dev->of_node; in imx_pcie_probe()
1484 return -ENOMEM; in imx_pcie_probe()
1488 return -ENOMEM; in imx_pcie_probe()
1490 pci->dev = dev; in imx_pcie_probe()
1491 pci->ops = &dw_pcie_ops; in imx_pcie_probe()
1493 imx_pcie->pci = pci; in imx_pcie_probe()
1494 imx_pcie->drvdata = of_device_get_match_data(dev); in imx_pcie_probe()
1496 mutex_init(&imx_pcie->lock); in imx_pcie_probe()
1498 if (imx_pcie->drvdata->ops) in imx_pcie_probe()
1499 pci->pp.ops = imx_pcie->drvdata->ops; in imx_pcie_probe()
1501 pci->pp.ops = &imx_pcie_host_dw_pme_ops; in imx_pcie_probe()
1504 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); in imx_pcie_probe()
1513 imx_pcie->phy_base = devm_ioremap_resource(dev, &res); in imx_pcie_probe()
1514 if (IS_ERR(imx_pcie->phy_base)) in imx_pcie_probe()
1515 return PTR_ERR(imx_pcie->phy_base); in imx_pcie_probe()
1518 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); in imx_pcie_probe()
1519 if (IS_ERR(pci->dbi_base)) in imx_pcie_probe()
1520 return PTR_ERR(pci->dbi_base); in imx_pcie_probe()
1523 imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); in imx_pcie_probe()
1524 if (IS_ERR(imx_pcie->reset_gpiod)) in imx_pcie_probe()
1525 return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod), in imx_pcie_probe()
1526 "unable to get reset gpio\n"); in imx_pcie_probe()
1527 gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); in imx_pcie_probe()
1529 if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS) in imx_pcie_probe()
1530 return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); in imx_pcie_probe()
1532 for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) in imx_pcie_probe()
1533 imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; in imx_pcie_probe()
1536 req_cnt = imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optional_cnt; in imx_pcie_probe()
1537 ret = devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); in imx_pcie_probe()
1540 imx_pcie->clks[req_cnt].clk = devm_clk_get_optional(dev, "ref"); in imx_pcie_probe()
1541 if (IS_ERR(imx_pcie->clks[req_cnt].clk)) in imx_pcie_probe()
1542 return PTR_ERR(imx_pcie->clks[req_cnt].clk); in imx_pcie_probe()
1545 imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); in imx_pcie_probe()
1546 if (IS_ERR(imx_pcie->phy)) in imx_pcie_probe()
1547 return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), in imx_pcie_probe()
1552 imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); in imx_pcie_probe()
1553 if (IS_ERR(imx_pcie->apps_reset)) in imx_pcie_probe()
1554 return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), in imx_pcie_probe()
1555 "failed to get pcie apps reset control\n"); in imx_pcie_probe()
1559 imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); in imx_pcie_probe()
1560 if (IS_ERR(imx_pcie->pciephy_reset)) in imx_pcie_probe()
1561 return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), in imx_pcie_probe()
1562 "Failed to get PCIEPHY reset control\n"); in imx_pcie_probe()
1565 switch (imx_pcie->drvdata->variant) { in imx_pcie_probe()
1568 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) in imx_pcie_probe()
1569 imx_pcie->controller_id = 1; in imx_pcie_probe()
1575 if (imx_pcie->drvdata->gpr) { in imx_pcie_probe()
1577 imx_pcie->iomuxc_gpr = in imx_pcie_probe()
1578 syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); in imx_pcie_probe()
1579 if (IS_ERR(imx_pcie->iomuxc_gpr)) in imx_pcie_probe()
1580 return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), in imx_pcie_probe()
1597 imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); in imx_pcie_probe()
1598 if (IS_ERR(imx_pcie->iomuxc_gpr)) in imx_pcie_probe()
1599 return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), in imx_pcie_probe()
1604 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", in imx_pcie_probe()
1605 &imx_pcie->tx_deemph_gen1)) in imx_pcie_probe()
1606 imx_pcie->tx_deemph_gen1 = 0; in imx_pcie_probe()
1608 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", in imx_pcie_probe()
1609 &imx_pcie->tx_deemph_gen2_3p5db)) in imx_pcie_probe()
1610 imx_pcie->tx_deemph_gen2_3p5db = 0; in imx_pcie_probe()
1612 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", in imx_pcie_probe()
1613 &imx_pcie->tx_deemph_gen2_6db)) in imx_pcie_probe()
1614 imx_pcie->tx_deemph_gen2_6db = 20; in imx_pcie_probe()
1616 if (of_property_read_u32(node, "fsl,tx-swing-full", in imx_pcie_probe()
1617 &imx_pcie->tx_swing_full)) in imx_pcie_probe()
1618 imx_pcie->tx_swing_full = 127; in imx_pcie_probe()
1620 if (of_property_read_u32(node, "fsl,tx-swing-low", in imx_pcie_probe()
1621 &imx_pcie->tx_swing_low)) in imx_pcie_probe()
1622 imx_pcie->tx_swing_low = 127; in imx_pcie_probe()
1625 pci->max_link_speed = 1; in imx_pcie_probe()
1626 of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed); in imx_pcie_probe()
1628 imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); in imx_pcie_probe()
1629 if (IS_ERR(imx_pcie->vpcie)) { in imx_pcie_probe()
1630 if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) in imx_pcie_probe()
1631 return PTR_ERR(imx_pcie->vpcie); in imx_pcie_probe()
1632 imx_pcie->vpcie = NULL; in imx_pcie_probe()
1635 imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); in imx_pcie_probe()
1636 if (IS_ERR(imx_pcie->vph)) { in imx_pcie_probe()
1637 if (PTR_ERR(imx_pcie->vph) != -ENODEV) in imx_pcie_probe()
1638 return PTR_ERR(imx_pcie->vph); in imx_pcie_probe()
1639 imx_pcie->vph = NULL; in imx_pcie_probe()
1648 if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { in imx_pcie_probe()
1653 pci->pp.use_atu_msg = true; in imx_pcie_probe()
1654 ret = dw_pcie_host_init(&pci->pp); in imx_pcie_probe()
1693 .gpr = "fsl,imx6q-iomuxc-gpr",
1709 .gpr = "fsl,imx6q-iomuxc-gpr",
1727 .gpr = "fsl,imx6q-iomuxc-gpr",
1744 .gpr = "fsl,imx7d-iomuxc-gpr",
1757 .gpr = "fsl,imx8mq-iomuxc-gpr",
1772 .gpr = "fsl,imx8mm-iomuxc-gpr",
1784 .gpr = "fsl,imx8mp-iomuxc-gpr",
1818 .gpr = "fsl,imx8mq-iomuxc-gpr",
1834 .gpr = "fsl,imx8mm-iomuxc-gpr",
1847 .gpr = "fsl,imx8mp-iomuxc-gpr",
1880 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1881 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1882 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1883 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1884 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1885 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1886 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1887 { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], },
1888 { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
1889 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1890 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1891 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1892 { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
1893 { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
1899 .name = "imx6q-pcie",
1911 struct pci_bus *bus = dev->bus; in imx_pcie_quirk()
1912 struct dw_pcie_rp *pp = bus->sysdata; in imx_pcie_quirk()
1915 if (!bus->dev.parent || !bus->dev.parent->parent) in imx_pcie_quirk()
1919 if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) in imx_pcie_quirk()
1930 if (imx_pcie->drvdata->dbi_length) { in imx_pcie_quirk()
1931 dev->cfg_size = imx_pcie->drvdata->dbi_length; in imx_pcie_quirk()
1932 dev_info(&dev->dev, "Limiting cfg_size to %d\n", in imx_pcie_quirk()
1933 dev->cfg_size); in imx_pcie_quirk()
1947 return -ENODEV; in imx_pcie_init()
1953 * by kernel and since imx6q_pcie_abort_handler() is a no-op, in imx_pcie_init()
1958 "external abort on non-linefetch"); in imx_pcie_init()