Lines Matching +full:0 +full:x64e00000
25 * base+0 data
33 * base+0x400 ECP config A
34 * base+0x401 ECP config B
35 * base+0x402 ECP control
42 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
85 #define ECR_MODE_MASK 0xe0
86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
95 } superios[NR_SUPERIOS] = { {0,},};
111 unsigned char ectr = 0; in frob_econtrol()
114 if (m != 0xff) in frob_econtrol()
119 /* All known users of the ECR mask require bit 0 to be set. */ in frob_econtrol()
135 0 : Success
145 pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m); in change_mode()
149 return 0; in change_mode()
154 mode = (oecr >> 5) & 0x7; in change_mode()
156 return 0; in change_mode()
158 if (mode >= 2 && !(priv->ctr & 0x20)) { in change_mode()
167 for (counter = 0; counter < 40; counter++) { in change_mode()
168 if (inb(ECONTROL(p)) & 0x01) in change_mode()
176 while (!(inb(ECONTROL(p)) & 0x01)) { in change_mode()
199 return 0; in change_mode()
212 if (!(parport_pc_read_status(pb) & 0x01)) in clear_epp_timeout()
218 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */ in clear_epp_timeout()
219 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */ in clear_epp_timeout()
222 return !(r & 0x01); in clear_epp_timeout()
236 s->u.pc.ctr = 0xc; in parport_pc_init_state()
240 s->u.pc.ctr |= 0x10; in parport_pc_init_state()
242 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; in parport_pc_init_state()
269 size_t got = 0; in parport_pc_epp_read_data()
276 * nFault is 0 if there is at least 1 byte in the Warp's FIFO in parport_pc_epp_read_data()
281 while (!(status & 0x08) && got < length) { in parport_pc_epp_read_data()
282 if (left >= 16 && (status & 0x20) && !(status & 0x08)) { in parport_pc_epp_read_data()
284 if (!((long)buf & 0x03)) in parport_pc_epp_read_data()
299 if (status & 0x01) { in parport_pc_epp_read_data()
312 && !(((long)buf | length) & 0x03)) in parport_pc_epp_read_data()
315 && !(((long)buf | length) & 0x01)) in parport_pc_epp_read_data()
319 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_data()
328 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_data()
341 size_t written = 0; in parport_pc_epp_write_data()
347 && !(((long)buf | length) & 0x03)) in parport_pc_epp_write_data()
350 && !(((long)buf | length) & 0x01)) in parport_pc_epp_write_data()
354 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_data()
363 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_data()
375 size_t got = 0; in parport_pc_epp_read_addr()
379 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_addr()
388 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_addr()
401 size_t written = 0; in parport_pc_epp_write_addr()
405 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_addr()
414 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_addr()
430 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_read_data()
444 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_write_data()
459 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_read_addr()
473 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_write_addr()
486 int ret = 0; in parport_pc_fifo_write_block_pio()
508 int i = 0; in parport_pc_fifo_write_block_pio()
520 if (ecrval & 0x02) { in parport_pc_fifo_write_block_pio()
527 if (ret < 0) in parport_pc_fifo_write_block_pio()
529 ret = 0; in parport_pc_fifo_write_block_pio()
554 if (ecrval & 0x01) { in parport_pc_fifo_write_block_pio()
584 int ret = 0; in parport_pc_fifo_write_block_dma()
590 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ in parport_pc_fifo_write_block_dma()
597 if ((start ^ end) & ~0xffffUL) in parport_pc_fifo_write_block_dma()
598 maxlen = 0x10000 - (start & 0xffff); in parport_pc_fifo_write_block_dma()
607 dma_handle = 0; in parport_pc_fifo_write_block_dma()
642 frob_econtrol(port, 1<<2, 0); in parport_pc_fifo_write_block_dma()
656 if (ret < 0) in parport_pc_fifo_write_block_dma()
658 ret = 0; in parport_pc_fifo_write_block_dma()
700 frob_econtrol(port, 1<<3, 0); in parport_pc_fifo_write_block_dma()
738 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0); in parport_pc_compat_write_block_pio()
770 if (inb(ECONTROL(port)) & 0x2) { in parport_pc_compat_write_block_pio()
774 outb(0, FIFO(port)); in parport_pc_compat_write_block_pio()
834 0); in parport_pc_ecp_write_block_pio()
865 if (inb(ECONTROL(port)) & 0x2) { in parport_pc_ecp_write_block_pio()
869 outb(0, FIFO(port)); in parport_pc_ecp_write_block_pio()
878 parport_frob_control(port, PARPORT_CONTROL_INIT, 0); in parport_pc_ecp_write_block_pio()
879 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); in parport_pc_ecp_write_block_pio()
959 for (i = 0; i < NR_SUPERIOS; i++) in find_free_superio()
960 if (superios[i].io == 0) in find_free_superio()
984 outb(0x0a, io); in show_parconfig_smsc37c669()
986 outb(0x23, io); in show_parconfig_smsc37c669()
988 outb(0x26, io); in show_parconfig_smsc37c669()
990 outb(0x27, io); in show_parconfig_smsc37c669()
992 outb(0xaa, io); in show_parconfig_smsc37c669()
995 …pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n… in show_parconfig_smsc37c669()
1001 pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", in show_parconfig_smsc37c669()
1003 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', in show_parconfig_smsc37c669()
1004 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', in show_parconfig_smsc37c669()
1005 cra & 0x0f); in show_parconfig_smsc37c669()
1007 (cr23 * 4 >= 0x100) ? "yes" : "no", in show_parconfig_smsc37c669()
1010 (cr1 & 0x08) ? "Standard mode only (SPP)" in show_parconfig_smsc37c669()
1011 : modes[cr4 & 0x03], in show_parconfig_smsc37c669()
1012 (cr4 & 0x40) ? "1.7" : "1.9"); in show_parconfig_smsc37c669()
1019 if (cr23 * 4 >= 0x100) { /* if active */ in show_parconfig_smsc37c669()
1026 case 0x3bc: in show_parconfig_smsc37c669()
1027 s->io = 0x3bc; in show_parconfig_smsc37c669()
1030 case 0x378: in show_parconfig_smsc37c669()
1031 s->io = 0x378; in show_parconfig_smsc37c669()
1034 case 0x278: in show_parconfig_smsc37c669()
1035 s->io = 0x278; in show_parconfig_smsc37c669()
1038 d = (cr26 & 0x0f); in show_parconfig_smsc37c669()
1053 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ in show_parconfig_winbond()
1070 outb(0x07, io); /* Register 7: Select Logical Device */ in show_parconfig_winbond()
1071 outb(0x01, io + 1); /* LD1 is Parallel Port */ in show_parconfig_winbond()
1072 outb(0x30, io); in show_parconfig_winbond()
1074 outb(0x60, io); in show_parconfig_winbond()
1076 outb(0x61, io); in show_parconfig_winbond()
1078 outb(0x70, io); in show_parconfig_winbond()
1080 outb(0x74, io); in show_parconfig_winbond()
1082 outb(0xf0, io); in show_parconfig_winbond()
1084 outb(0xaa, io); in show_parconfig_winbond()
1089 pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", in show_parconfig_winbond()
1090 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); in show_parconfig_winbond()
1091 if ((cr74 & 0x07) > 3) in show_parconfig_winbond()
1094 pr_cont("dma=%d\n", cr74 & 0x07); in show_parconfig_winbond()
1096 irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f); in show_parconfig_winbond()
1098 modes[crf0 & 0x07]); in show_parconfig_winbond()
1101 if (cr30 & 0x01) { /* the settings can be interrogated later ... */ in show_parconfig_winbond()
1107 s->irq = cr70 & 0x0f; in show_parconfig_winbond()
1108 s->dma = (((cr74 & 0x07) > 3) ? in show_parconfig_winbond()
1109 PARPORT_DMA_NONE : (cr74 & 0x07)); in show_parconfig_winbond()
1128 if (id == 0x9771) in decode_winbond()
1130 else if (id == 0x9773) in decode_winbond()
1132 else if (id == 0x9774) in decode_winbond()
1134 else if ((id & ~0x0f) == 0x5270) in decode_winbond()
1136 else if ((id & ~0x0f) == 0x52f0) in decode_winbond()
1138 else if ((id & ~0x0f) == 0x5210) in decode_winbond()
1140 else if ((id & ~0x0f) == 0x6010) in decode_winbond()
1142 else if ((oldid & 0x0f) == 0x0a) { in decode_winbond()
1145 } else if ((oldid & 0x0f) == 0x0b) { in decode_winbond()
1148 } else if ((oldid & 0x0f) == 0x0c) { in decode_winbond()
1151 } else if ((oldid & 0x0f) == 0x0d) { in decode_winbond()
1155 progif = 0; in decode_winbond()
1158 pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n", in decode_winbond()
1179 if (id == 0x0302) { in decode_smsc()
1182 } else if (id == 0x6582) in decode_smsc()
1184 else if (devid == 0x65) in decode_smsc()
1186 else if (devid == 0x66) in decode_smsc()
1190 pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n", in decode_smsc()
1208 outb(0x20, io); in winbond_check()
1210 outb(0x21, io); in winbond_check()
1212 outb(0x09, io); in winbond_check()
1218 outb(0x20, io); /* Write EFIR, extended function index register */ in winbond_check()
1220 outb(0x21, io); in winbond_check()
1222 outb(0x09, io); in winbond_check()
1224 outb(0xaa, io); /* Magic Seal */ in winbond_check()
1243 origval[0] = inb(io); /* Save original values */ in winbond_check2()
1248 outb(0x20, io + 2); in winbond_check2()
1250 outb(0x21, io + 1); in winbond_check2()
1252 outb(0x09, io + 1); in winbond_check2()
1257 outb(0x20, io + 2); /* Write EFIR, extended function index register */ in winbond_check2()
1259 outb(0x21, io + 1); in winbond_check2()
1261 outb(0x09, io + 1); in winbond_check2()
1263 outb(0xaa, io); /* Magic Seal */ in winbond_check2()
1265 outb(origval[0], io); /* in case we poked some entirely different hardware */ in winbond_check2()
1287 outb(0x0d, io); in smsc_check()
1289 outb(0x0e, io); in smsc_check()
1291 outb(0x20, io); in smsc_check()
1293 outb(0x21, io); in smsc_check()
1299 outb(0x0d, io); /* Write EFIR, extended function index register */ in smsc_check()
1301 outb(0x0e, io); in smsc_check()
1303 outb(0x20, io); in smsc_check()
1305 outb(0x21, io); in smsc_check()
1307 outb(0xaa, io); /* Magic Seal */ in smsc_check()
1325 winbond_check(0x3f0, 0x87); in detect_and_report_winbond()
1326 winbond_check(0x370, 0x87); in detect_and_report_winbond()
1327 winbond_check(0x2e , 0x87); in detect_and_report_winbond()
1328 winbond_check(0x4e , 0x87); in detect_and_report_winbond()
1329 winbond_check(0x3f0, 0x86); in detect_and_report_winbond()
1330 winbond_check2(0x250, 0x88); in detect_and_report_winbond()
1331 winbond_check2(0x250, 0x89); in detect_and_report_winbond()
1338 smsc_check(0x3f0, 0x55); in detect_and_report_smsc()
1339 smsc_check(0x370, 0x55); in detect_and_report_smsc()
1340 smsc_check(0x3f0, 0x44); in detect_and_report_smsc()
1341 smsc_check(0x370, 0x44); in detect_and_report_smsc()
1350 if (!request_muxed_region(0x2e, 2, __func__)) in detect_and_report_it87()
1352 origval = inb(0x2e); /* Save original value */ in detect_and_report_it87()
1353 outb(0x87, 0x2e); in detect_and_report_it87()
1354 outb(0x01, 0x2e); in detect_and_report_it87()
1355 outb(0x55, 0x2e); in detect_and_report_it87()
1356 outb(0x55, 0x2e); in detect_and_report_it87()
1357 outb(0x20, 0x2e); in detect_and_report_it87()
1358 dev = inb(0x2f) << 8; in detect_and_report_it87()
1359 outb(0x21, 0x2e); in detect_and_report_it87()
1360 dev |= inb(0x2f); in detect_and_report_it87()
1361 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || in detect_and_report_it87()
1362 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { in detect_and_report_it87()
1364 outb(0x07, 0x2E); /* Parallel Port */ in detect_and_report_it87()
1365 outb(0x03, 0x2F); in detect_and_report_it87()
1366 outb(0xF0, 0x2E); /* BOOT 0x80 off */ in detect_and_report_it87()
1367 r = inb(0x2f); in detect_and_report_it87()
1368 outb(0xF0, 0x2E); in detect_and_report_it87()
1369 outb(r | 8, 0x2F); in detect_and_report_it87()
1370 outb(0x02, 0x2E); /* Lock */ in detect_and_report_it87()
1371 outb(0x02, 0x2F); in detect_and_report_it87()
1373 outb(origval, 0x2e); /* Oops, sorry to disturb */ in detect_and_report_it87()
1375 release_region(0x2e, 2); in detect_and_report_it87()
1382 for (i = 0; i < NR_SUPERIOS; i++) in find_superio()
1410 * 0 : No parallel port at this address
1429 w = 0xc; in parport_SPP_supported()
1438 if ((r & 0xf) == w) { in parport_SPP_supported()
1439 w = 0xe; in parport_SPP_supported()
1442 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1443 if ((r & 0xf) == w) in parport_SPP_supported()
1450 pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n", in parport_SPP_supported()
1455 w = 0xaa; in parport_SPP_supported()
1459 w = 0x55; in parport_SPP_supported()
1469 pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n", in parport_SPP_supported()
1471 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n", in parport_SPP_supported()
1480 return 0; in parport_SPP_supported()
1485 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1488 * Modern cards don't do this but reading from ECR will return 0xff
1499 unsigned char r = 0xc; in parport_ECR_present()
1503 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { in parport_ECR_present()
1504 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ in parport_ECR_present()
1507 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) in parport_ECR_present()
1512 if ((inb(ECONTROL(pb)) & 0x3) != 0x1) in parport_ECR_present()
1515 ECR_WRITE(pb, 0x34); in parport_ECR_present()
1516 if (inb(ECONTROL(pb)) != 0x35) in parport_ECR_present()
1521 outb(0xc, CONTROL(pb)); in parport_ECR_present()
1529 outb(0xc, CONTROL(pb)); in parport_ECR_present()
1530 return 0; in parport_ECR_present()
1536 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1538 * 0xff but any peripheral attached to the port may drag some or all of the
1553 int ok = 0; in parport_PS2_supported()
1560 parport_pc_write_data(pb, 0x55); in parport_PS2_supported()
1561 if (parport_pc_read_data(pb) != 0x55) in parport_PS2_supported()
1564 parport_pc_write_data(pb, 0xaa); in parport_PS2_supported()
1565 if (parport_pc_read_data(pb) != 0xaa) in parport_PS2_supported()
1575 priv->ctr_writable &= ~0x20; in parport_PS2_supported()
1589 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 }; in parport_ECP_supported()
1593 return 0; in parport_ECP_supported()
1598 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) in parport_ECP_supported()
1599 outb(0xaa, FIFO(pb)); in parport_ECP_supported()
1607 return 0; in parport_ECP_supported()
1612 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); in parport_ECP_supported()
1616 frob_econtrol(pb, 1<<2, 0); in parport_ECP_supported()
1626 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", in parport_ECP_supported()
1631 i = 0; in parport_ECP_supported()
1640 frob_econtrol(pb, 1<<2, 0); in parport_ECP_supported()
1642 outb(0xaa, FIFO(pb)); in parport_ECP_supported()
1649 pr_info("0x%lx: readIntrThreshold is %d\n", in parport_ECP_supported()
1653 i = 0; in parport_ECP_supported()
1658 ECR_WRITE(pb, 0xf4); /* Configuration mode */ in parport_ECP_supported()
1660 pword = (config >> 4) & 0x7; in parport_ECP_supported()
1662 case 0: in parport_ECP_supported()
1664 pr_warn("0x%lx: Unsupported pword size!\n", pb->base); in parport_ECP_supported()
1668 pr_warn("0x%lx: Unsupported pword size!\n", pb->base); in parport_ECP_supported()
1671 pr_warn("0x%lx: Unknown implementation ID\n", pb->base); in parport_ECP_supported()
1679 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", in parport_ECP_supported()
1682 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", in parport_ECP_supported()
1683 pb->base, config & 0x80 ? "Level" : "Pulses"); in parport_ECP_supported()
1686 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", in parport_ECP_supported()
1688 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); in parport_ECP_supported()
1689 if ((configb >> 3) & 0x07) in parport_ECP_supported()
1690 pr_cont("%d", intrline[(configb >> 3) & 0x07]); in parport_ECP_supported()
1694 if ((configb & 0x03) == 0x00) in parport_ECP_supported()
1697 pr_cont("%d\n", configb & 0x07); in parport_ECP_supported()
1711 int bug_present = 0; in intel_bug_present_check_epp()
1717 for (i = 0x00; i < 0x80; i += 0x20) { in intel_bug_present_check_epp()
1735 return 0; in intel_bug_present()
1743 return 0; in intel_bug_present()
1754 return 0; in parport_ECPPS2_supported()
1769 * Bit 0 of STR is the EPP timeout bit, this bit is 0 in parport_EPP_supported()
1782 return 0; /* No way to clear timeout */ in parport_EPP_supported()
1786 return 0; in parport_EPP_supported()
1806 return 0; in parport_ECPEPP_supported()
1810 ECR_WRITE(pb, 0x80); in parport_ECPEPP_supported()
1811 outb(0x04, CONTROL(pb)); in parport_ECPEPP_supported()
1830 static int parport_PS2_supported(struct parport *pb) { return 0; } in parport_PS2_supported()
1834 return 0; in parport_ECP_supported()
1839 return 0; in parport_EPP_supported()
1844 return 0; in parport_ECPEPP_supported()
1849 return 0; in parport_ECPPS2_supported()
1867 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; in programmable_irq_support()
1882 ECR_WRITE(pb, (ECR_TST << 5) | 0x04); in irq_probe_ECP()
1886 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) in irq_probe_ECP()
1887 outb(0xaa, FIFO(pb)); in irq_probe_ECP()
1892 if (pb->irq <= 0) in irq_probe_ECP()
1916 frob_econtrol(pb, 0x10, 0x10); in irq_probe_EPP()
1919 parport_pc_frob_control(pb, 0x20, 0x20); in irq_probe_EPP()
1920 parport_pc_frob_control(pb, 0x10, 0x10); in irq_probe_EPP()
1932 parport_pc_write_control(pb, 0xc); in irq_probe_EPP()
1934 if (pb->irq <= 0) in irq_probe_EPP()
1995 dma = inb(CONFIGB(p)) & 0x07; in programmable_dma_support()
1998 if ((dma & 0x03) == 0) in programmable_dma_support()
2047 base, NULL, 0); in __parport_pc_probe_port()
2077 priv->ctr = 0xc; in __parport_pc_probe_port()
2078 priv->ctr_writable = ~0x10; in __parport_pc_probe_port()
2079 priv->ecr = 0; in __parport_pc_probe_port()
2081 priv->fifo_depth = 0; in __parport_pc_probe_port()
2083 priv->dma_handle = 0; in __parport_pc_probe_port()
2098 if (base != 0x3bc) { in __parport_pc_probe_port()
2099 EPP_res = request_region(base+0x3, 5, p->name); in __parport_pc_probe_port()
2114 pr_info("%s: PC-style at 0x%lx", p->name, p->base); in __parport_pc_probe_port()
2116 pr_cont(" (0x%lx)", p->base_hi); in __parport_pc_probe_port()
2128 priv->ctr_writable |= 0x10; in __parport_pc_probe_port()
2142 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { in __parport_pc_probe_port()
2154 if ((p->modes & PARPORT_MODE_COMPAT) != 0) in __parport_pc_probe_port()
2157 if ((p->modes & PARPORT_MODE_ECP) != 0) in __parport_pc_probe_port()
2160 if ((p->modes & (PARPORT_MODE_ECP | PARPORT_MODE_COMPAT)) != 0) { in __parport_pc_probe_port()
2161 if ((p->modes & PARPORT_MODE_DMA) != 0) in __parport_pc_probe_port()
2174 } while (0) in __parport_pc_probe_port()
2177 int f = 0; in __parport_pc_probe_port()
2194 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { in __parport_pc_probe_port()
2199 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { in __parport_pc_probe_port()
2243 ECR_WRITE(p, 0x34); in __parport_pc_probe_port()
2245 parport_pc_write_data(p, 0); in __parport_pc_probe_port()
2262 release_region(base+0x3, 5); in __parport_pc_probe_port()
2283 dev, irqflags, 0, 0); in parport_pc_probe_port()
2325 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; in sio_ite_8872_probe()
2335 for (i = 0; i < 5; i++) { in sio_ite_8872_probe()
2338 pci_write_config_dword(pdev, 0x60, in sio_ite_8872_probe()
2339 0xe5000000 | inta_addr[i]); in sio_ite_8872_probe()
2340 pci_write_config_dword(pdev, 0x78, in sio_ite_8872_probe()
2341 0x00000000 | inta_addr[i]); in sio_ite_8872_probe()
2343 if (test != 0xff) in sio_ite_8872_probe()
2350 return 0; in sio_ite_8872_probe()
2353 type = inb(inta_addr[i] + 0x18); in sio_ite_8872_probe()
2354 type &= 0x0f; in sio_ite_8872_probe()
2357 case 0x2: in sio_ite_8872_probe()
2359 ite8872set = 0x64200000; in sio_ite_8872_probe()
2361 case 0xa: in sio_ite_8872_probe()
2363 ite8872set = 0x64200000; in sio_ite_8872_probe()
2365 case 0xe: in sio_ite_8872_probe()
2367 ite8872set = 0x64e00000; in sio_ite_8872_probe()
2369 case 0x6: in sio_ite_8872_probe()
2372 return 0; in sio_ite_8872_probe()
2373 case 0x8: in sio_ite_8872_probe()
2376 return 0; in sio_ite_8872_probe()
2381 return 0; in sio_ite_8872_probe()
2384 pci_read_config_byte(pdev, 0x3c, &ite8872_irq); in sio_ite_8872_probe()
2385 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt); in sio_ite_8872_probe()
2386 ite8872_lpt &= 0x0000ff00; in sio_ite_8872_probe()
2387 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi); in sio_ite_8872_probe()
2388 ite8872_lpthi &= 0x0000ff00; in sio_ite_8872_probe()
2389 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt); in sio_ite_8872_probe()
2390 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi); in sio_ite_8872_probe()
2391 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); in sio_ite_8872_probe()
2394 pci_write_config_dword(pdev, 0x9c, in sio_ite_8872_probe()
2395 ite8872set | (ite8872_irq * 0x11111)); in sio_ite_8872_probe()
2398 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt); in sio_ite_8872_probe()
2399 pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi); in sio_ite_8872_probe()
2411 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { in sio_ite_8872_probe()
2412 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X", in sio_ite_8872_probe()
2420 return 0; in sio_ite_8872_probe()
2429 0x51,
2430 0x50,
2431 0x85,
2432 0x02,
2433 0xE2,
2434 0xF0,
2435 0xE6
2438 0x45,
2439 0x44,
2440 0x50,
2441 0x04,
2442 0xF2,
2443 0xFA,
2444 0xF6
2451 u8 ppcontrol = 0; in sio_via_probe()
2454 unsigned have_epp = 0; in sio_via_probe()
2497 /* Bits 1-0: Parallel Port Mode / Enable */ in sio_via_probe()
2521 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", in sio_via_probe()
2523 if (port1 == 0x3BC && have_epp) { in sio_via_probe()
2525 outb((0x378 >> 2), VIA_CONFIG_DATA); in sio_via_probe()
2526 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); in sio_via_probe()
2527 port1 = 0x378; in sio_via_probe()
2539 return 0; in sio_via_probe()
2564 case 0x3bc: in sio_via_probe()
2565 port2 = 0x7bc; break; in sio_via_probe()
2566 case 0x378: in sio_via_probe()
2567 port2 = 0x778; break; in sio_via_probe()
2568 case 0x278: in sio_via_probe()
2569 port2 = 0x678; break; in sio_via_probe()
2571 pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n", in sio_via_probe()
2573 return 0; in sio_via_probe()
2578 case 0: in sio_via_probe()
2590 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { in sio_via_probe()
2591 pr_info("parport_pc: VIA parallel port: io=0x%X", port1); in sio_via_probe()
2600 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", in sio_via_probe()
2602 return 0; in sio_via_probe()
2607 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2681 * case additionally bit 0 will be forcibly set on writes. */
2695 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2696 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2697 /* lava_parallel */ { 1, { { 0, -1 }, } },
2698 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2699 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2700 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2702 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2703 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2704 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2705 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2706 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2709 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2710 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2712 /* avlab_1p */ { 1, { { 0, 1}, } },
2713 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2717 * bit pattern to be used for bits 4:0 with ECR writes. */
2718 /* oxsemi_952 */ { 1, { { 0, 1 }, },
2720 /* oxsemi_954 */ { 1, { { 0, 1 }, },
2723 /* oxsemi_840 */ { 1, { { 0, 1 }, },
2725 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, },
2727 /* aks_0100 */ { 1, { { 0, -1 }, } },
2728 /* mobility_pp */ { 1, { { 0, 1 }, } },
2729 /* netmos_9900 */ { 1, { { 0, -1 }, } },
2732 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2733 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2734 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2735 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2736 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2737 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2738 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2739 /* asix_ax99100 */ { 1, { { 0, 1 }, } },
2740 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2743 /* brainboxes_px203 */ { 1, { { 0, -1 }, } },
2748 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2749 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2771 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2773 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2774 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2775 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2776 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2777 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2786 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2787 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2812 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2815 0xA000, 0x2000, 0, 0, netmos_9900 },
2817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2827 0xA000, 0x2000, 0, 0, netmos_9901 },
2829 0xA000, 0x1000, 0, 0, netmos_9865 },
2831 0xA000, 0x2000, 0, 0, netmos_9865 },
2834 0xA000, 0x2000, 0, 0, asix_ax99100 },
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2839 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
2841 { PCI_VENDOR_ID_INTASHIELD, 0x402a,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2844 { PCI_VENDOR_ID_INTASHIELD, 0x0be1,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 },
2846 { PCI_VENDOR_ID_INTASHIELD, 0x0be2,
2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 },
2849 { PCI_VENDOR_ID_INTASHIELD, 0x401c,
2850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2852 { PCI_VENDOR_ID_INTASHIELD, 0x4007,
2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_px203 },
2855 { PCI_VENDOR_ID_INTASHIELD, 0x401f,
2856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2857 { 0, } /* terminate list */
2874 return 0; in parport_pc_pci_probe()
2878 count = 0; in parport_pc_pci_probe()
2893 for (n = 0; n < cards[i].numports; n++) { in parport_pc_pci_probe()
2899 io_hi = 0; in parport_pc_pci_probe()
2900 if ((hi >= 0) && (hi <= 6)) in parport_pc_pci_probe()
2929 cards[i].postinit_hook(dev, count == 0); in parport_pc_pci_probe()
2933 return 0; in parport_pc_pci_probe()
2947 for (i = data->num - 1; i >= 0; i--) in parport_pc_pci_remove()
2965 int ret = 0; in parport_pc_init_superio()
2985 return 0; in parport_pc_init_superio()
2993 {.id = "PNP0400", .driver_data = 0},
2995 {.id = "PNP0401", .driver_data = 0},
3008 if (pnp_port_valid(dev, 0) && in parport_pc_pnp_probe()
3009 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { in parport_pc_pnp_probe()
3010 io_lo = pnp_port_start(dev, 0); in parport_pc_pnp_probe()
3018 io_hi = 0; in parport_pc_pnp_probe()
3020 if (pnp_irq_valid(dev, 0) && in parport_pc_pnp_probe()
3021 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) { in parport_pc_pnp_probe()
3022 irq = pnp_irq(dev, 0); in parport_pc_pnp_probe()
3026 if (pnp_dma_valid(dev, 0) && in parport_pc_pnp_probe()
3027 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) { in parport_pc_pnp_probe()
3028 dma = pnp_dma(dev, 0); in parport_pc_pnp_probe()
3033 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0); in parport_pc_pnp_probe()
3038 return 0; in parport_pc_pnp_probe()
3066 return 0; in parport_pc_platform_probe()
3080 int count = 0; in parport_pc_find_isa_ports()
3082 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) in parport_pc_find_isa_ports()
3084 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) in parport_pc_find_isa_ports()
3086 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) in parport_pc_find_isa_ports()
3104 int count = 0, err; in parport_pc_find_ports()
3137 [0 ... PARPORT_PC_MAX_PORTS] = 0
3140 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3143 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3146 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3153 return 0; in parport_parse_param()
3162 unsigned long r = simple_strtoul(s, &ep, 0); in parport_parse_param()
3170 return 0; in parport_parse_param()
3176 PARPORT_IRQ_NONE, 0); in parport_parse_irq()
3210 module_param_hw_array(io, int, ioport, NULL, 0);
3212 module_param_hw_array(io_hi, int, ioport, NULL, 0);
3214 module_param_hw_array(irq, charp, irq, NULL, 0);
3216 module_param_hw_array(dma, charp, dma, NULL, 0);
3226 module_param(init_mode, charp, 0);
3239 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { in parse_parport_params()
3247 if (!io[0]) { in parse_parport_params()
3249 if (irq[0] && !parport_parse_irq(irq[0], &val)) in parse_parport_params()
3253 irqval[0] = val; in parse_parport_params()
3259 if (dma[0] && !parport_parse_dma(dma[0], &val)) in parse_parport_params()
3263 dmaval[0] = val; in parse_parport_params()
3269 return 0; in parse_parport_params()
3279 * parport=0
3281 * parport=0xBASE[,IRQ[,DMA]]
3291 if (!str || !*str || (*str == '0' && !*(str+1))) { in parport_setup()
3292 /* Disable parport if "parport=0" in cmdline */ in parport_setup()
3293 io[0] = PARPORT_DISABLE; in parport_setup()
3298 irqval[0] = PARPORT_IRQ_AUTO; in parport_setup()
3299 dmaval[0] = PARPORT_DMA_AUTO; in parport_setup()
3303 val = simple_strtoul(str, &endptr, 0); in parport_setup()
3336 return io[0] == PARPORT_DISABLE; in parse_parport_params()
3364 if (io[0]) { in parport_pc_init()
3368 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { in parport_pc_init()
3372 io_hi[i] = 0x400 + io[i]; in parport_pc_init()
3374 irqval[i], dmaval[i], NULL, 0); in parport_pc_init()
3377 parport_pc_find_ports(irqval[0], dmaval[0]); in parport_pc_init()
3379 return 0; in parport_pc_init()