Lines Matching +full:0 +full:x27
26 memset(chip, 0, sizeof(*chip)); in zd_chip_init()
50 int i = 0; in scnprint_id()
73 buffer[sizeof(buffer)-1] = 0; in print_id()
82 if ((a & 0xf000) == CR_START) in inc_addr()
109 for (i = 0; i < count; i++) { in zd_ioread32v_locked()
123 for (i = 0; i < count; i++) { in zd_ioread32v_locked()
128 return 0; in zd_ioread32v_locked()
143 if (count == 0) in _zd_iowrite32v_async_locked()
144 return 0; in _zd_iowrite32v_async_locked()
151 for (i = 0; i < count; i++) { in _zd_iowrite32v_async_locked()
178 zd_usb_iowrite16v_async_end(&chip->usb, 0); in _zd_iowrite32v_locked()
193 for (i = 0; i < count; i += j + t) { in zd_iowrite16a_locked()
194 t = 0; in zd_iowrite16a_locked()
198 for (j = 0; j < max; j++) { in zd_iowrite16a_locked()
207 zd_usb_iowrite16v_async_end(&chip->usb, 0); in zd_iowrite16a_locked()
230 for (i = 0; i < count; i += j + t) { in zd_iowrite32a_locked()
231 t = 0; in zd_iowrite32a_locked()
235 for (j = 0; j < max; j++) { in zd_iowrite32a_locked()
244 zd_usb_iowrite16v_async_end(&chip->usb, 0); in zd_iowrite32a_locked()
329 *rf_type = value & 0x0f; in read_pod()
330 chip->pa_type = (value >> 16) & 0x0f; in read_pod()
331 chip->patch_cck_gain = (value >> 8) & 0x1; in read_pod()
332 chip->patch_cr157 = (value >> 13) & 0x1; in read_pod()
333 chip->patch_6m_band_edge = (value >> 21) & 0x1; in read_pod()
334 chip->new_phy_layout = (value >> 31) & 0x1; in read_pod()
335 chip->al2230s_bit = (value >> 7) & 0x1; in read_pod()
340 chip->supports_tx_led = 0; in read_pod()
352 return 0; in read_pod()
354 *rf_type = 0; in read_pod()
355 chip->pa_type = 0; in read_pod()
356 chip->patch_cck_gain = 0; in read_pod()
357 chip->patch_cr157 = 0; in read_pod()
358 chip->patch_6m_band_edge = 0; in read_pod()
359 chip->new_phy_layout = 0; in read_pod()
368 struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]}; in zd_write_mac_addr_common()
371 reqs[0].value = (mac_addr[3] << 24) in zd_write_mac_addr_common()
374 | mac_addr[0]; in zd_write_mac_addr_common()
394 [0] = { .addr = CR_MAC_ADDR_P1 }, in zd_write_mac_addr()
404 [0] = { .addr = CR_BSSID_P1 }, in zd_write_bssid()
425 return 0; in zd_read_regdomain()
436 for (i = 0;;) { in read_values()
451 return 0; in read_values()
459 0); in read_pwr_cal_values()
479 for (i = 0; i < 3; i++) { in read_ofdm_cal_values()
481 E2P_CHANNEL_COUNT, addresses[i], 0); in read_ofdm_cal_values()
485 return 0; in read_ofdm_cal_values()
501 return 0; in read_cal_int_tables()
553 return 0; in patch_cr157()
572 return 0; in patch_6m_band_edge()
582 { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, in zd_chip_generic_patch_6m_band()
583 { ZD_CR47, 0x1e }, in zd_chip_generic_patch_6m_band()
588 ioreqs[0].value = 0x12; in zd_chip_generic_patch_6m_band()
597 { ZD_CR0, 0x0a }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 }, in zd1211_hw_reset_phy()
598 { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xa0 }, in zd1211_hw_reset_phy()
599 { ZD_CR10, 0x81 }, { ZD_CR11, 0x00 }, { ZD_CR12, 0x7f }, in zd1211_hw_reset_phy()
600 { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, { ZD_CR15, 0x3d }, in zd1211_hw_reset_phy()
601 { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, { ZD_CR18, 0x0a }, in zd1211_hw_reset_phy()
602 { ZD_CR19, 0x48 }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0c }, in zd1211_hw_reset_phy()
603 { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, { ZD_CR24, 0x14 }, in zd1211_hw_reset_phy()
604 { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, { ZD_CR27, 0x19 }, in zd1211_hw_reset_phy()
605 { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, { ZD_CR30, 0x4b }, in zd1211_hw_reset_phy()
606 { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 }, in zd1211_hw_reset_phy()
607 { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 }, in zd1211_hw_reset_phy()
608 { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c }, in zd1211_hw_reset_phy()
609 { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 }, in zd1211_hw_reset_phy()
610 { ZD_CR43, 0x10 }, { ZD_CR44, 0x12 }, { ZD_CR46, 0xff }, in zd1211_hw_reset_phy()
611 { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b }, in zd1211_hw_reset_phy()
612 { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 }, in zd1211_hw_reset_phy()
613 { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 }, in zd1211_hw_reset_phy()
614 { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff }, in zd1211_hw_reset_phy()
615 { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 }, in zd1211_hw_reset_phy()
616 { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 }, in zd1211_hw_reset_phy()
617 { ZD_CR79, 0x68 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 }, in zd1211_hw_reset_phy()
618 { ZD_CR82, 0x00 }, { ZD_CR83, 0x00 }, { ZD_CR84, 0x00 }, in zd1211_hw_reset_phy()
619 { ZD_CR85, 0x02 }, { ZD_CR86, 0x00 }, { ZD_CR87, 0x00 }, in zd1211_hw_reset_phy()
620 { ZD_CR88, 0xff }, { ZD_CR89, 0xfc }, { ZD_CR90, 0x00 }, in zd1211_hw_reset_phy()
621 { ZD_CR91, 0x00 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x08 }, in zd1211_hw_reset_phy()
622 { ZD_CR94, 0x00 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0xff }, in zd1211_hw_reset_phy()
623 { ZD_CR97, 0xe7 }, { ZD_CR98, 0x00 }, { ZD_CR99, 0x00 }, in zd1211_hw_reset_phy()
624 { ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 }, in zd1211_hw_reset_phy()
625 { ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 }, in zd1211_hw_reset_phy()
626 { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a }, in zd1211_hw_reset_phy()
627 { ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 }, in zd1211_hw_reset_phy()
628 { ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e }, in zd1211_hw_reset_phy()
629 { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 }, in zd1211_hw_reset_phy()
631 { ZD_CR5, 0x00 }, { ZD_CR6, 0x00 }, { ZD_CR7, 0x00 }, in zd1211_hw_reset_phy()
632 { ZD_CR8, 0x00 }, { ZD_CR9, 0x20 }, { ZD_CR12, 0xf0 }, in zd1211_hw_reset_phy()
633 { ZD_CR20, 0x0e }, { ZD_CR21, 0x0e }, { ZD_CR27, 0x10 }, in zd1211_hw_reset_phy()
634 { ZD_CR44, 0x33 }, { ZD_CR47, 0x1E }, { ZD_CR83, 0x24 }, in zd1211_hw_reset_phy()
635 { ZD_CR84, 0x04 }, { ZD_CR85, 0x00 }, { ZD_CR86, 0x0C }, in zd1211_hw_reset_phy()
636 { ZD_CR87, 0x12 }, { ZD_CR88, 0x0C }, { ZD_CR89, 0x00 }, in zd1211_hw_reset_phy()
637 { ZD_CR90, 0x10 }, { ZD_CR91, 0x08 }, { ZD_CR93, 0x00 }, in zd1211_hw_reset_phy()
638 { ZD_CR94, 0x01 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0x50 }, in zd1211_hw_reset_phy()
639 { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, { ZD_CR101, 0x13 }, in zd1211_hw_reset_phy()
640 { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, in zd1211_hw_reset_phy()
641 { ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 }, in zd1211_hw_reset_phy()
642 { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, in zd1211_hw_reset_phy()
643 { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 }, in zd1211_hw_reset_phy()
644 { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f }, in zd1211_hw_reset_phy()
645 { ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 }, in zd1211_hw_reset_phy()
646 { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C }, in zd1211_hw_reset_phy()
647 { ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 }, in zd1211_hw_reset_phy()
648 { ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 }, in zd1211_hw_reset_phy()
649 { ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c }, in zd1211_hw_reset_phy()
650 { ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 }, in zd1211_hw_reset_phy()
651 { ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe }, in zd1211_hw_reset_phy()
652 { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa }, in zd1211_hw_reset_phy()
653 { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe }, in zd1211_hw_reset_phy()
654 { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba }, in zd1211_hw_reset_phy()
655 { ZD_CR170, 0xba }, { ZD_CR171, 0xba }, in zd1211_hw_reset_phy()
657 { ZD_CR204, 0x7d }, in zd1211_hw_reset_phy()
659 { ZD_CR203, 0x30 }, in zd1211_hw_reset_phy()
686 { ZD_CR0, 0x14 }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 }, in zd1211b_hw_reset_phy()
687 { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xe0 }, in zd1211b_hw_reset_phy()
688 { ZD_CR10, 0x81 }, in zd1211b_hw_reset_phy()
690 { ZD_CR11, 0x00 }, in zd1211b_hw_reset_phy()
691 { ZD_CR12, 0xf0 }, { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, in zd1211b_hw_reset_phy()
692 { ZD_CR15, 0x3d }, { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, in zd1211b_hw_reset_phy()
693 { ZD_CR18, 0x0a }, { ZD_CR19, 0x48 }, in zd1211b_hw_reset_phy()
694 { ZD_CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ in zd1211b_hw_reset_phy()
695 { ZD_CR21, 0x0e }, { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, in zd1211b_hw_reset_phy()
696 { ZD_CR24, 0x14 }, { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, in zd1211b_hw_reset_phy()
697 { ZD_CR27, 0x10 }, { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, in zd1211b_hw_reset_phy()
698 { ZD_CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ in zd1211b_hw_reset_phy()
699 { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 }, in zd1211b_hw_reset_phy()
700 { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 }, in zd1211b_hw_reset_phy()
701 { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c }, in zd1211b_hw_reset_phy()
702 { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 }, in zd1211b_hw_reset_phy()
703 { ZD_CR43, 0x10 }, { ZD_CR44, 0x33 }, { ZD_CR46, 0xff }, in zd1211b_hw_reset_phy()
704 { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b }, in zd1211b_hw_reset_phy()
705 { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 }, in zd1211b_hw_reset_phy()
706 { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 }, in zd1211b_hw_reset_phy()
707 { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff }, in zd1211b_hw_reset_phy()
708 { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 }, in zd1211b_hw_reset_phy()
709 { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 }, in zd1211b_hw_reset_phy()
710 { ZD_CR79, 0xf0 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 }, in zd1211b_hw_reset_phy()
711 { ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 }, in zd1211b_hw_reset_phy()
712 { ZD_CR85, 0x00 }, { ZD_CR86, 0x0c }, { ZD_CR87, 0x12 }, in zd1211b_hw_reset_phy()
713 { ZD_CR88, 0x0c }, { ZD_CR89, 0x00 }, { ZD_CR90, 0x58 }, in zd1211b_hw_reset_phy()
714 { ZD_CR91, 0x04 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x00 }, in zd1211b_hw_reset_phy()
715 { ZD_CR94, 0x01 }, in zd1211b_hw_reset_phy()
716 { ZD_CR95, 0x20 }, /* ZD1211B */ in zd1211b_hw_reset_phy()
717 { ZD_CR96, 0x50 }, { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, in zd1211b_hw_reset_phy()
718 { ZD_CR99, 0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 }, in zd1211b_hw_reset_phy()
719 { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, in zd1211b_hw_reset_phy()
720 { ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, in zd1211b_hw_reset_phy()
721 { ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 }, in zd1211b_hw_reset_phy()
722 { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, in zd1211b_hw_reset_phy()
723 { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 }, in zd1211b_hw_reset_phy()
724 { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e }, in zd1211b_hw_reset_phy()
725 { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 }, in zd1211b_hw_reset_phy()
726 { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, in zd1211b_hw_reset_phy()
727 { ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 }, in zd1211b_hw_reset_phy()
728 { ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 }, in zd1211b_hw_reset_phy()
729 { ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c }, in zd1211b_hw_reset_phy()
730 { ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 }, in zd1211b_hw_reset_phy()
731 { ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ in zd1211b_hw_reset_phy()
732 { ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ in zd1211b_hw_reset_phy()
733 { ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe }, in zd1211b_hw_reset_phy()
734 { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa }, in zd1211b_hw_reset_phy()
735 { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe }, in zd1211b_hw_reset_phy()
736 { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba }, in zd1211b_hw_reset_phy()
737 { ZD_CR170, 0xba }, { ZD_CR171, 0xba }, in zd1211b_hw_reset_phy()
739 { ZD_CR204, 0x7d }, in zd1211b_hw_reset_phy()
741 { ZD_CR203, 0x30 }, in zd1211b_hw_reset_phy()
770 { CR_RX_THRESHOLD, 0x000c0640 }, in zd1211_hw_init_hmac()
782 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f }, in zd1211b_hw_init_hmac()
783 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f }, in zd1211b_hw_init_hmac()
784 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f }, in zd1211b_hw_init_hmac()
785 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f }, in zd1211b_hw_init_hmac()
786 { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, in zd1211b_hw_init_hmac()
787 { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, in zd1211b_hw_init_hmac()
788 { CR_ZD1211B_TXOP, 0x01800824 }, in zd1211b_hw_init_hmac()
789 { CR_RX_THRESHOLD, 0x000c0eff, }, in zd1211b_hw_init_hmac()
801 { CR_ACK_TIMEOUT_EXT, 0x20 }, in hw_init_hmac()
802 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, in hw_init_hmac()
803 { CR_SNIFFER_ON, 0 }, in hw_init_hmac()
805 { CR_GROUP_HASH_P1, 0x00 }, in hw_init_hmac()
806 { CR_GROUP_HASH_P2, 0x80000000 }, in hw_init_hmac()
807 { CR_REG1, 0xa4 }, in hw_init_hmac()
808 { CR_ADDA_PWR_DWN, 0x7f }, in hw_init_hmac()
809 { CR_BCN_PLCP_CFG, 0x00f00401 }, in hw_init_hmac()
810 { CR_PHY_DELAY, 0x00 }, in hw_init_hmac()
811 { CR_ACK_TIMEOUT_EXT, 0x80 }, in hw_init_hmac()
812 { CR_ADDA_PWR_DWN, 0x00 }, in hw_init_hmac()
813 { CR_ACK_TIME_80211, 0x100 }, in hw_init_hmac()
814 { CR_RX_PE_DELAY, 0x70 }, in hw_init_hmac()
815 { CR_PS_CTRL, 0x10000000 }, in hw_init_hmac()
816 { CR_RTS_CTS_RATE, 0x02030203 }, in hw_init_hmac()
817 { CR_AFTER_PNP, 0x1 }, in hw_init_hmac()
818 { CR_WEP_PROTECT, 0x114 }, in hw_init_hmac()
848 memset(s, 0, sizeof(*s)); in get_aw_pt_bi()
852 s->atim_wnd_period = values[0]; in get_aw_pt_bi()
855 return 0; in get_aw_pt_bi()
861 u16 b_interval = s->beacon_interval & 0xffff; in set_aw_pt_bi()
870 reqs[0].addr = CR_ATIM_WND_PERIOD; in set_aw_pt_bi()
871 reqs[0].value = s->atim_wnd_period; in set_aw_pt_bi()
875 reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval; in set_aw_pt_bi()
890 if (interval > 0) { in set_beacon_interval()
900 mode_flag = 0; in set_beacon_interval()
904 dtim_period = 0; in set_beacon_interval()
905 mode_flag = 0; in set_beacon_interval()
944 return set_beacon_interval(chip, 100, 0, NL80211_IFTYPE_UNSPECIFIED); in hw_init()
968 return 0; in dump_cr()
1004 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); in dump_fw_registers()
1027 return 0; in print_fw_version()
1050 u32 value = 0; in zd_chip_set_rts_cts_rate_locked()
1102 return 0; in read_fw_regs_offset()
1137 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); in zd_chip_init_hw()
1202 ioreqs[0].addr = ZD_CR67; in update_ofdm_cal()
1203 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; in update_ofdm_cal()
1218 return 0; in update_channel_integration_and_calibration()
1225 { ZD_CR69, 0x28 }, in update_channel_integration_and_calibration()
1227 { ZD_CR69, 0x2a }, in update_channel_integration_and_calibration()
1241 return 0; in update_channel_integration_and_calibration()
1251 return 0; in patch_cck_gain()
1257 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); in patch_cck_gain()
1258 return zd_iowrite16_locked(chip, value & 0xff, ZD_CR47); in patch_cck_gain()
1281 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); in zd_chip_set_channel()
1311 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, in zd_chip_control_leds()
1325 ioreqs[0].value = FW_LINK_OFF; in zd_chip_control_leds()
1329 ioreqs[0].value = FW_LINK_OFF; in zd_chip_control_leds()
1331 if ((u32)ktime_get_seconds() % 3 == 0) { in zd_chip_control_leds()
1338 ioreqs[0].value = FW_LINK_TX; in zd_chip_control_leds()
1347 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { in zd_chip_control_leds()
1352 r = 0; in zd_chip_control_leds()
1404 zd_rate = 0; in zd_rx_rate()
1478 for (i = 0; i < count; i++) { in zd_rfwritev_locked()
1484 return 0; in zd_rfwritev_locked()
1494 { ZD_CR244, (value >> 16) & 0xff }, in zd_rfwrite_cr_locked()
1495 { ZD_CR243, (value >> 8) & 0xff }, in zd_rfwrite_cr_locked()
1496 { ZD_CR242, value & 0xff }, in zd_rfwrite_cr_locked()
1508 for (i = 0; i < count; i++) { in zd_rfwritev_cr_locked()
1514 return 0; in zd_rfwritev_cr_locked()
1541 return 0; in zd_chip_get_tsf()
1544 tsf = (tsf << 32) | values[0]; in zd_chip_get_tsf()