Lines Matching +full:boot +full:- +full:blks
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2010 Nokia Corporation
20 #include "../wlcore/boot.h"
280 .rssi_threshold = -90,
415 /* TI-specific rate */
445 /* TI-specific rate */
589 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
590 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
591 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
593 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
594 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
595 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
601 if (wl->chip.id != CHIP_ID_128X_PG20) { in wl127x_prepare_read()
602 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map; in wl127x_prepare_read()
603 struct wl12xx_priv *priv = wl->priv; in wl127x_prepare_read()
612 priv->rx_mem_addr->addr = (mem_block << 8) + in wl127x_prepare_read()
613 le32_to_cpu(wl_mem_map->packet_memory_pool_start); in wl127x_prepare_read()
615 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4; in wl127x_prepare_read()
617 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr, in wl127x_prepare_read()
618 sizeof(*priv->rx_mem_addr), false); in wl127x_prepare_read()
630 switch (wl->chip.id) { in wl12xx_identify_chip()
633 wl->chip.id); in wl12xx_identify_chip()
635 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS | in wl12xx_identify_chip()
639 wl->sr_fw_name = WL127X_FW_NAME_SINGLE; in wl12xx_identify_chip()
640 wl->mr_fw_name = WL127X_FW_NAME_MULTI; in wl12xx_identify_chip()
641 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x, in wl12xx_identify_chip()
642 sizeof(wl->conf.mem)); in wl12xx_identify_chip()
645 wl->ops->prepare_read = wl127x_prepare_read; in wl12xx_identify_chip()
656 wl->chip.id); in wl12xx_identify_chip()
658 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS | in wl12xx_identify_chip()
662 wl->plt_fw_name = WL127X_PLT_FW_NAME; in wl12xx_identify_chip()
663 wl->sr_fw_name = WL127X_FW_NAME_SINGLE; in wl12xx_identify_chip()
664 wl->mr_fw_name = WL127X_FW_NAME_MULTI; in wl12xx_identify_chip()
665 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x, in wl12xx_identify_chip()
666 sizeof(wl->conf.mem)); in wl12xx_identify_chip()
669 wl->ops->prepare_read = wl127x_prepare_read; in wl12xx_identify_chip()
680 wl->chip.id); in wl12xx_identify_chip()
681 wl->plt_fw_name = WL128X_PLT_FW_NAME; in wl12xx_identify_chip()
682 wl->sr_fw_name = WL128X_FW_NAME_SINGLE; in wl12xx_identify_chip()
683 wl->mr_fw_name = WL128X_FW_NAME_MULTI; in wl12xx_identify_chip()
686 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN | in wl12xx_identify_chip()
699 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); in wl12xx_identify_chip()
700 ret = -ENODEV; in wl12xx_identify_chip()
704 wl->fw_mem_block_size = 256; in wl12xx_identify_chip()
705 wl->fwlog_end = 0x2000000; in wl12xx_identify_chip()
708 wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY; in wl12xx_identify_chip()
709 wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY; in wl12xx_identify_chip()
710 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4; in wl12xx_identify_chip()
711 wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5; in wl12xx_identify_chip()
712 wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ; in wl12xx_identify_chip()
713 wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS; in wl12xx_identify_chip()
766 } while (!(val & OCP_READY_MASK) && --timeout); in wl12xx_top_reg_read()
770 return -ETIMEDOUT; in wl12xx_top_reg_read()
776 return -EIO; in wl12xx_top_reg_read()
796 return -EFAULT; in wl128x_switch_tcxo_to_fref()
868 struct wl12xx_priv *priv = wl->priv; in wl128x_configure_mcs_pll()
877 return -EFAULT; in wl128x_configure_mcs_pll()
884 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 || in wl128x_configure_mcs_pll()
885 priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6) in wl128x_configure_mcs_pll()
896 return -EFAULT; in wl128x_configure_mcs_pll()
905 * WL128x has two clocks input - TCXO and FREF.
913 struct wl12xx_priv *priv = wl->priv; in wl128x_boot_clk()
917 /* For XTAL-only modes, FREF will be used after switching from TCXO */ in wl128x_boot_clk()
918 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL || in wl128x_boot_clk()
919 priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) { in wl128x_boot_clk()
921 return -EINVAL; in wl128x_boot_clk()
931 return -EINVAL; in wl128x_boot_clk()
936 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 || in wl128x_boot_clk()
937 priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) { in wl128x_boot_clk()
939 return -EINVAL; in wl128x_boot_clk()
945 return -EINVAL; in wl128x_boot_clk()
946 *selected_clock = priv->tcxo_clock; in wl128x_boot_clk()
952 return -EINVAL; in wl128x_boot_clk()
953 *selected_clock = priv->ref_clock; in wl128x_boot_clk()
961 struct wl12xx_priv *priv = wl->priv; in wl127x_boot_clk()
966 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3) in wl127x_boot_clk()
967 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION; in wl127x_boot_clk()
969 if (priv->ref_clock == CONF_REF_CLK_19_2_E || in wl127x_boot_clk()
970 priv->ref_clock == CONF_REF_CLK_38_4_E || in wl127x_boot_clk()
971 priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL) in wl127x_boot_clk()
972 /* ref clk: 19.2/38.4/38.4-XTAL */ in wl127x_boot_clk()
974 else if (priv->ref_clock == CONF_REF_CLK_26_E || in wl127x_boot_clk()
975 priv->ref_clock == CONF_REF_CLK_26_M_XTAL || in wl127x_boot_clk()
976 priv->ref_clock == CONF_REF_CLK_52_E) in wl127x_boot_clk()
980 return -EINVAL; in wl127x_boot_clk()
982 if (priv->ref_clock != CONF_REF_CLK_19_2_E) { in wl127x_boot_clk()
1058 /* 1.2 check pWhalBus->uSelfClearTime if the in wl1271_boot_soft_reset()
1061 return -1; in wl1271_boot_soft_reset()
1081 struct wl12xx_priv *priv = wl->priv; in wl12xx_pre_boot()
1084 int selected_clock = -1; in wl12xx_pre_boot()
1086 if (wl->chip.id == CHIP_ID_128X_PG20) { in wl12xx_pre_boot()
1103 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]); in wl12xx_pre_boot()
1107 /* Read-modify-write DRPW_SCRATCH_START register (see next state) in wl12xx_pre_boot()
1117 if (wl->chip.id == CHIP_ID_128X_PG20) in wl12xx_pre_boot()
1120 clk |= (priv->ref_clock << 1) << 4; in wl12xx_pre_boot()
1126 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]); in wl12xx_pre_boot()
1171 if (wl->chip.id == CHIP_ID_128X_PG20) { in wl12xx_pre_upload()
1238 wl->event_mask = BSS_LOSE_EVENT_ID | in wl12xx_boot()
1254 wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID; in wl12xx_boot()
1291 return (align_len + blk_size - 1) / blk_size + spare_blks; in wl12xx_calc_tx_blocks()
1296 u32 blks, u32 spare_blks) in wl12xx_set_tx_desc_blocks() argument
1298 if (wl->chip.id == CHIP_ID_128X_PG20) { in wl12xx_set_tx_desc_blocks()
1299 desc->wl128x_mem.total_mem_blocks = blks; in wl12xx_set_tx_desc_blocks()
1301 desc->wl127x_mem.extra_blocks = spare_blks; in wl12xx_set_tx_desc_blocks()
1302 desc->wl127x_mem.total_mem_blocks = blks; in wl12xx_set_tx_desc_blocks()
1310 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len); in wl12xx_set_tx_desc_data_len()
1312 if (wl->chip.id == CHIP_ID_128X_PG20) { in wl12xx_set_tx_desc_data_len()
1313 desc->wl128x_mem.extra_bytes = aligned_len - skb->len; in wl12xx_set_tx_desc_data_len()
1314 desc->length = cpu_to_le16(aligned_len >> 2); in wl12xx_set_tx_desc_data_len()
1318 desc->hlid, in wl12xx_set_tx_desc_data_len()
1319 le16_to_cpu(desc->length), in wl12xx_set_tx_desc_data_len()
1320 le16_to_cpu(desc->life_time), in wl12xx_set_tx_desc_data_len()
1321 desc->wl128x_mem.total_mem_blocks, in wl12xx_set_tx_desc_data_len()
1322 desc->wl128x_mem.extra_bytes); in wl12xx_set_tx_desc_data_len()
1325 int pad = aligned_len - skb->len; in wl12xx_set_tx_desc_data_len()
1326 desc->tx_attr |= in wl12xx_set_tx_desc_data_len()
1330 desc->length = cpu_to_le16(aligned_len >> 2); in wl12xx_set_tx_desc_data_len()
1334 pad, desc->hlid, in wl12xx_set_tx_desc_data_len()
1335 le16_to_cpu(desc->length), in wl12xx_set_tx_desc_data_len()
1336 le16_to_cpu(desc->life_time), in wl12xx_set_tx_desc_data_len()
1337 desc->wl127x_mem.total_mem_blocks); in wl12xx_set_tx_desc_data_len()
1357 data_len < sizeof(*desc) + desc->pad_len) in wl12xx_get_rx_packet_len()
1360 return data_len - sizeof(*desc) - desc->pad_len; in wl12xx_get_rx_packet_len()
1365 if (wl->fw_status->tx_results_counter == in wl12xx_tx_delayed_compl()
1366 (wl->tx_results_count & 0xff)) in wl12xx_tx_delayed_compl()
1376 if (wl->chip.id == CHIP_ID_128X_PG20) { in wl12xx_hw_init()
1385 * in wl->fem_manuf. No need to continue further in wl12xx_hw_init()
1387 if (wl->plt_mode == PLT_FEM_DETECT) in wl12xx_hw_init()
1394 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) in wl12xx_hw_init()
1409 * in wl->fem_manuf. No need to continue further in wl12xx_hw_init()
1411 if (wl->plt_mode == PLT_FEM_DETECT) in wl12xx_hw_init()
1430 fw_status->intr = le32_to_cpu(int_fw_status->intr); in wl12xx_convert_fw_status()
1431 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter; in wl12xx_convert_fw_status()
1432 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter; in wl12xx_convert_fw_status()
1433 fw_status->tx_results_counter = int_fw_status->tx_results_counter; in wl12xx_convert_fw_status()
1434 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs; in wl12xx_convert_fw_status()
1436 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime); in wl12xx_convert_fw_status()
1437 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap); in wl12xx_convert_fw_status()
1438 fw_status->link_fast_bitmap = in wl12xx_convert_fw_status()
1439 le32_to_cpu(int_fw_status->link_fast_bitmap); in wl12xx_convert_fw_status()
1440 fw_status->total_released_blks = in wl12xx_convert_fw_status()
1441 le32_to_cpu(int_fw_status->total_released_blks); in wl12xx_convert_fw_status()
1442 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total); in wl12xx_convert_fw_status()
1444 fw_status->counters.tx_released_pkts = in wl12xx_convert_fw_status()
1445 int_fw_status->counters.tx_released_pkts; in wl12xx_convert_fw_status()
1446 fw_status->counters.tx_lnk_free_pkts = in wl12xx_convert_fw_status()
1447 int_fw_status->counters.tx_lnk_free_pkts; in wl12xx_convert_fw_status()
1448 fw_status->counters.tx_voice_released_blks = in wl12xx_convert_fw_status()
1449 int_fw_status->counters.tx_voice_released_blks; in wl12xx_convert_fw_status()
1450 fw_status->counters.tx_last_rate = in wl12xx_convert_fw_status()
1451 int_fw_status->counters.tx_last_rate; in wl12xx_convert_fw_status()
1453 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr); in wl12xx_convert_fw_status()
1459 return wlvif->rate_set; in wl12xx_sta_get_ap_rate_mask()
1464 struct wl12xx_priv *priv = wl->priv; in wl12xx_conf_init()
1467 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf)); in wl12xx_conf_init()
1470 memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf)); in wl12xx_conf_init()
1478 if (wl->chip.id == CHIP_ID_128X_PG20) { in wl12xx_mac_in_fuse()
1479 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver); in wl12xx_mac_in_fuse()
1480 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver); in wl12xx_mac_in_fuse()
1486 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver); in wl12xx_mac_in_fuse()
1487 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver); in wl12xx_mac_in_fuse()
1513 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]); in wl12xx_get_fuse_mac()
1526 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + in wl12xx_get_fuse_mac()
1528 wl->fuse_nic_addr = mac1 & 0xffffff; in wl12xx_get_fuse_mac()
1530 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); in wl12xx_get_fuse_mac()
1541 if (wl->chip.id == CHIP_ID_128X_PG20) in wl12xx_get_pg_ver()
1566 desc->wl12xx_reserved = 0; in wl12xx_set_tx_desc_csum()
1573 ret = wl->ops->boot(wl); in wl12xx_plt_init()
1577 ret = wl->ops->hw_init(wl); in wl12xx_plt_init()
1583 * in wl->fem_manuf. No need to continue further in wl12xx_plt_init()
1585 if (wl->plt_mode == PLT_FEM_DETECT) in wl12xx_plt_init()
1614 kfree(wl->target_mem_map); in wl12xx_plt_init()
1615 wl->target_mem_map = NULL; in wl12xx_plt_init()
1618 mutex_unlock(&wl->mutex); in wl12xx_plt_init()
1627 mutex_lock(&wl->mutex); in wl12xx_plt_init()
1662 if (test_bit(hlid, &wl->fw_fast_lnk_map)) in wl12xx_lnk_high_prio()
1663 thold = wl->conf.tx.fast_link_thold; in wl12xx_lnk_high_prio()
1665 thold = wl->conf.tx.slow_link_thold; in wl12xx_lnk_high_prio()
1667 return lnk->allocated_pkts < thold; in wl12xx_lnk_high_prio()
1687 .boot = wl12xx_boot,
1794 return -EINVAL; in wl12xx_get_clock_idx()
1799 struct wl12xx_priv *priv = wl->priv; in wl12xx_setup()
1800 struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev); in wl12xx_setup()
1806 wl->rtable = wl12xx_rtable; in wl12xx_setup()
1807 wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS; in wl12xx_setup()
1808 wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS; in wl12xx_setup()
1809 wl->num_links = WL12XX_MAX_LINKS; in wl12xx_setup()
1810 wl->max_ap_stations = WL12XX_MAX_AP_STATIONS; in wl12xx_setup()
1811 wl->iface_combinations = wl12xx_iface_combinations; in wl12xx_setup()
1812 wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations); in wl12xx_setup()
1813 wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES; in wl12xx_setup()
1814 wl->band_rate_to_idx = wl12xx_band_rate_to_idx; in wl12xx_setup()
1815 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX; in wl12xx_setup()
1816 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0; in wl12xx_setup()
1817 wl->fw_status_len = sizeof(struct wl12xx_fw_status); in wl12xx_setup()
1818 wl->fw_status_priv_len = 0; in wl12xx_setup()
1819 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics); in wl12xx_setup()
1820 wl->ofdm_only_ap = true; in wl12xx_setup()
1826 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table, in wl12xx_setup()
1827 pdev_data->ref_clock_freq, in wl12xx_setup()
1828 pdev_data->ref_clock_xtal); in wl12xx_setup()
1829 if (priv->ref_clock < 0) { in wl12xx_setup()
1831 pdev_data->ref_clock_freq, in wl12xx_setup()
1832 pdev_data->ref_clock_xtal ? in wl12xx_setup()
1835 return priv->ref_clock; in wl12xx_setup()
1839 priv->ref_clock = WL12XX_REFCLOCK_19; in wl12xx_setup()
1841 priv->ref_clock = WL12XX_REFCLOCK_26; in wl12xx_setup()
1843 priv->ref_clock = WL12XX_REFCLOCK_26_XTAL; in wl12xx_setup()
1845 priv->ref_clock = WL12XX_REFCLOCK_38; in wl12xx_setup()
1847 priv->ref_clock = WL12XX_REFCLOCK_38_XTAL; in wl12xx_setup()
1849 priv->ref_clock = WL12XX_REFCLOCK_52; in wl12xx_setup()
1854 if (!tcxo_param && pdev_data->tcxo_clock_freq) { in wl12xx_setup()
1855 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table, in wl12xx_setup()
1856 pdev_data->tcxo_clock_freq, in wl12xx_setup()
1858 if (priv->tcxo_clock < 0) { in wl12xx_setup()
1860 pdev_data->tcxo_clock_freq); in wl12xx_setup()
1862 return priv->tcxo_clock; in wl12xx_setup()
1866 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2; in wl12xx_setup()
1868 priv->tcxo_clock = WL12XX_TCXOCLOCK_26; in wl12xx_setup()
1870 priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4; in wl12xx_setup()
1872 priv->tcxo_clock = WL12XX_TCXOCLOCK_52; in wl12xx_setup()
1874 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368; in wl12xx_setup()
1876 priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736; in wl12xx_setup()
1878 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8; in wl12xx_setup()
1880 priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6; in wl12xx_setup()
1885 priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL); in wl12xx_setup()
1886 if (!priv->rx_mem_addr) in wl12xx_setup()
1887 return -ENOMEM; in wl12xx_setup()
1907 wl = hw->priv; in wl12xx_probe()
1908 wl->ops = &wl12xx_ops; in wl12xx_probe()
1909 wl->ptable = wl12xx_ptable; in wl12xx_probe()
1927 priv = wl->priv; in wl12xx_remove()
1929 kfree(priv->rx_mem_addr); in wl12xx_remove()