Lines Matching +full:gemini +full:- +full:pci
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
98 Host Interrupt Mask Register - 32bit (RW)
99 ------------------------------------------
102 0 - RX0 - Rx first dubble buffer Data Interrupt
103 1 - TXD - Tx Data Interrupt
104 2 - TXXFR - Tx Transfer Interrupt
105 3 - RX1 - Rx second dubble buffer Data Interrupt
106 4 - RXXFR - Rx Transfer Interrupt
107 5 - EVENT_A - Event Mailbox interrupt
108 6 - EVENT_B - Event Mailbox interrupt
109 7 - WNONHST - Wake On Host Interrupt
110 8 - TRACE_A - Debug Trace interrupt
111 9 - TRACE_B - Debug Trace interrupt
112 10 - CDCMP - Command Complete Interrupt
113 11 -
114 12 -
115 13 -
116 14 - ICOMP - Initialization Complete Interrupt
117 16 - SG SE - Soft Gemini - Sense enable interrupt
118 17 - SG SD - Soft Gemini - Sense disable interrupt
119 18 - -
120 19 - -
121 20 - -
122 21- -
129 ------------------------------------------
139 ------------------------------------------
150 ------------------------------------------
161 ------------------------------------------
172 ------------------------------------------
177 assotiated interrupt inactive. (0-no effect)
182 Host Software Reset - 32bit RW
183 ------------------------------------------
185 0 SOFT_RESET Soft Reset - When this bit is set,
188 clocks except the CardBus/PCI interface clock.
192 (not self-clearing), the Wlan hardware
198 EEPROM Burst Read Start - 32bit RW
199 ------------------------------------------
201 0 ACX_EE_START - EEPROM Burst Read Start 0
217 Halt eCPU - 32bit RW
218 ------------------------------------------
219 0 HALT_ECPU Halt Embedded CPU - This bit is the
226 zero-wait-state SSRAM.
230 --------------------
245 Command Mailbox Pointer - 32bit RW
246 ------------------------------------------
260 Information Mailbox Pointer - 32bit RW
261 ------------------------------------------
280 * ---------------------------------------------
288 /* promiscuous - receives all valid frames */
351 ------------------------------------------
352 1 EE_READ - EEPROM Read Request 1 - Setting this bit
359 0 EE_WRITE - EEPROM Write Request - Setting this bit
370 EEPROM Address - 32bit RW
371 ------------------------------------------
379 EEPROM Data - 32bit RW
380 ------------------------------------------
392 EEPROM Base Address - 32bit RW
393 ------------------------------------------
395 [23:15] of the 24-bit Wlan hardware memory
403 GPIO Output Values -32bit, RW
404 ------------------------------------------
413 Contention window -32bit, RW
414 ------------------------------------------
418 [06:00] Current contention window value - default is 0x1F
426 ------------------------------------------
562 Transmit-Descriptor RATE-SET field definitions...
564 Define a new "Rate-Set" for TX path that incorporates the
565 Rate & Modulation info into a single 16-bit field.
568 b15 - Indicates Preamble type (1=SHORT, 0=LONG).
571 Does not apply (set to 0) for RevG-OFDM rates.
572 b14 - Indicates PBCC encoding (1=PBCC, 0=not).
575 Does not apply (set to 0) for RevG-OFDM rates.
576 b13 - Unused (set to 0).
577 b12-b0 - Supported Rate indicator bits as defined below.
584 Interrupt Trigger Register (Host -> WiLink)
588 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
625 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */