1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
24 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;  in rtw89_pci_aspm_set_be()
25 	struct pci_dev *pdev = rtwpci->pdev;  in rtw89_pci_aspm_set_be()
80 	const struct rtw89_pci_info *info = rtwdev->pci_info;  in rtw89_pci_set_io_rcy_be()
84 	if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) {  in rtw89_pci_set_io_rcy_be()
85 		val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?  in rtw89_pci_set_io_rcy_be()
86 			PL0_TMR_ANA_172US : info->io_rcy_tmr;  in rtw89_pci_set_io_rcy_be()
98 		val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?  in rtw89_pci_set_io_rcy_be()
99 			PL0_TMR_MAC_1MS : info->io_rcy_tmr;  in rtw89_pci_set_io_rcy_be()
104 		val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?  in rtw89_pci_set_io_rcy_be()
105 			PL0_TMR_AUX_1MS : info->io_rcy_tmr;  in rtw89_pci_set_io_rcy_be()
164 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;  in rtw89_pci_clr_idx_all_be()
178 	rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ];  in rtw89_pci_clr_idx_all_be()
179 	rtw89_write16(rtwdev, R_BE_RXQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1);  in rtw89_pci_clr_idx_all_be()
181 	rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];  in rtw89_pci_clr_idx_all_be()
182 	rtw89_write16(rtwdev, R_BE_RPQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1);  in rtw89_pci_clr_idx_all_be()
225 	const struct rtw89_pci_info *info = rtwdev->pci_info;  in rtw89_pci_mode_op_be()
232 	if (info->rxbd_mode == MAC_AX_RXBD_PKT) {  in rtw89_pci_mode_op_be()
235 	} else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {  in rtw89_pci_mode_op_be()
242 	val32_init1 = u32_replace_bits(val32_init1, info->tx_burst,  in rtw89_pci_mode_op_be()
244 	val32_init1 = u32_replace_bits(val32_init1, info->rx_burst,  in rtw89_pci_mode_op_be()
246 	val32_exp = u32_replace_bits(val32_exp, info->multi_tag_num,  in rtw89_pci_mode_op_be()
248 	val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_idle_intvl,  in rtw89_pci_mode_op_be()
250 	val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_act_intvl,  in rtw89_pci_mode_op_be()
292 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_pci_pcie_setting_be()
293 	struct rtw89_hal *hal = &rtwdev->hal;  in rtw89_pci_pcie_setting_be()
298 	if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV)  in rtw89_pci_pcie_setting_be()
415 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
418 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
421 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
424 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
427 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
430 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
433 		return -EINVAL;  in rtw89_pci_ltr_set_v2()
475 	cnt = min_t(u32, U8_MAX, RTW89_PCI_RXBD_NUM_MAX / 2);  in rtw89_pci_configure_mit_be()
477 	val = u32_replace_bits(val, 2, B_BE_PCIE_RX_MIT0_TMR_CNT_MASK);  in rtw89_pci_configure_mit_be()
483 	const struct rtw89_pci_info *info = rtwdev->pci_info;  in rtw89_pci_ops_mac_post_init_be()
486 	ret = info->ltr_set(rtwdev, true);  in rtw89_pci_ops_mac_post_init_be()
558 	u8 gen;  in rtw89_pci_disable_eq_be()  local
560 	if (rtwdev->chip->chip_id != RTL8922A)  in rtw89_pci_disable_eq_be()
574 	for (gen = 1; gen <= 2; gen++) {  in rtw89_pci_disable_eq_be()
575 		phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :  in rtw89_pci_disable_eq_be()
585 	for (gen = 1; gen <= 2; gen++) {  in rtw89_pci_disable_eq_be()
586 		phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :  in rtw89_pci_disable_eq_be()
596 	for (gen = 1; gen <= 2; gen++) {  in rtw89_pci_disable_eq_be()
597 		phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :  in rtw89_pci_disable_eq_be()
613 	for (gen = 1; gen <= 2; gen++) {  in rtw89_pci_disable_eq_be()
614 		phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :  in rtw89_pci_disable_eq_be()
629 	struct rtw89_dev *rtwdev = hw->priv;  in rtw89_pci_suspend_be()
642 	struct rtw89_dev *rtwdev = hw->priv;  in rtw89_pci_resume_be()