Lines Matching +full:0 +full:x18800000
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
14 #define BSSID_CAM_ENT_SIZE 0x08
19 RTW89_DMAC_SEL = 0,
26 RTW89_FWD_DONT_CARE = 0,
42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
54 RTW89_MAC_TAG_NUM_DEF = 0xFE
58 RTW89_MAC_LBC_TMR_8US = 0,
69 RTW89_MAC_LBC_TMR_DEF = 0xFE
73 CPUIO_OP_CMD_GET_1ST_PID = 0,
83 WDE_DLE_PORT_ID_DISPATCH = 0,
93 WDE_DLE_QUEID_TXOK = 0,
101 PLE_DLE_PORT_ID_DISPATCH = 0,
113 PLE_DLE_QUEID_NO_REPORT = 0x0
117 RTW89_MGNT = 0,
123 DLE_DFI_TYPE_FREEPG = 0,
134 WDE_QTAID_HOST_IF = 0,
142 PLE_QTAID_B0_TXPL = 0,
156 DLE_CTRL_TYPE_WDE = 0,
162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
173 MAC_AX_PHY_RPT_SIZE_0 = 0,
180 MAC_AX_HDR_CNV_SIZE_0 = 0,
187 WOWLAN_NOT_READY = 0x00,
188 WOWLAN_SLEEP_READY = 0x01,
189 WOWLAN_RESUME_READY = 0x02,
195 /* CMAC 0 related */
196 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
298 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
299 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
301 #define AXIDMA_BASE_ADDR 0x18006000
302 #define STA_SCHED_BASE_ADDR 0x18808000
303 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
304 #define SECURITY_CAM_BASE_ADDR 0x18814000
305 #define WOW_CAM_BASE_ADDR 0x18815000
306 #define CMAC_TBL_BASE_ADDR 0x18840000
307 #define ADDR_CAM_BASE_ADDR 0x18850000
308 #define BSSID_CAM_BASE_ADDR 0x18853000
309 #define BA_CAM_BASE_ADDR 0x18854000
310 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
311 #define SHARED_BUF_BASE_ADDR 0x18700000
312 #define DMAC_TBL_BASE_ADDR 0x18800000
313 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
314 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
315 #define TXD_FIFO_0_BASE_ADDR 0x18856200
316 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
317 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
318 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
319 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
320 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
321 #define CPU_LOCAL_BASE_ADDR 0x18003000
323 #define WD_PAGE_BASE_ADDR_BE 0x0
324 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
325 #define AXIDMA_BASE_ADDR_BE 0x18006000
326 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
327 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
328 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
329 #define STA_SCHED_BASE_ADDR_BE 0x18818000
330 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
331 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
332 #define SEC_CAM_BASE_ADDR_BE 0x18824000
333 #define WOW_CAM_BASE_ADDR_BE 0x18828000
334 #define MLD_TBL_BASE_ADDR_BE 0x18829000
335 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
336 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
337 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
338 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
339 #define BA_CAM_BASE_ADDR_BE 0x18859000
340 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
341 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
342 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
343 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
344 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
345 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
346 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
379 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
406 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
407 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
408 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa,
409 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
422 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
431 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
444 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0,
450 RTW89_MAC_C2H_CLASS_INFO = 0x0,
451 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
452 RTW89_MAC_C2H_CLASS_TWT = 0x2,
453 RTW89_MAC_C2H_CLASS_WOW = 0x3,
454 RTW89_MAC_C2H_CLASS_MCC = 0x4,
455 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
456 RTW89_MAC_C2H_CLASS_MRC = 0xe,
457 RTW89_MAC_C2H_CLASS_AP = 0x18,
462 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
487 RTW89_MAC_MRC_START_SCH_OK = 0,
503 #define RTW89_MAC_AX_COEX_RTK_MODE 0
506 #define RTW89_MAC_AX_COEX_INNER 0
513 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
523 RTW89_MAC_BF_RRSC_6M = 0,
558 #define RTW89_R32_EA 0xEAEAEAEA
559 #define RTW89_R32_DEAD 0xDEADBEEF
564 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
565 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
579 #define S_AX_WDE_PAGE_SEL_64 0
587 #define S_AX_PLE_PAGE_SEL_64 0
603 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
605 #define SDIO_LOCAL_BASE_ADDR 0x80000000
607 #define PWR_CMD_WRITE 0
612 #define PWR_INTF_MSK_SDIO BIT(0)
615 #define PWR_INTF_MSK_ALL 0x7
617 #define PWR_BASE_MAC 0
622 #define PWR_CV_MSK_A BIT(0)
630 #define PWR_CV_MSK_ALL 0xFF
632 #define PWR_DELAY_US 0
637 #define SS_TX_LEN_MSK 0x1FFFFF
643 #define TMAC_DBG_SEL_C0 0xA5
644 #define RMAC_DBG_SEL_C0 0xA6
645 #define TRXPTCL_DBG_SEL_C0 0xA7
646 #define TMAC_DBG_SEL_C1 0xB5
647 #define RMAC_DBG_SEL_C1 0xB6
648 #define TRXPTCL_DBG_SEL_C1 0xB7
649 #define FW_PROG_CNTR_DBG_SEL 0xF2
650 #define PCIE_TXDMA_DBG_SEL 0x30
651 #define PCIE_RXDMA_DBG_SEL 0x31
652 #define PCIE_CVT_DBG_SEL 0x32
653 #define PCIE_CXPL_DBG_SEL 0x33
654 #define PCIE_IO_DBG_SEL 0x37
655 #define PCIE_MISC_DBG_SEL 0x38
656 #define PCIE_MISC2_DBG_SEL 0x00
661 #define TRXPTRL_DBG_SEL_TMAC 0
688 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
689 #define QLNKTBL_ADDR_INFO_SEL_0 0
692 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
743 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
744 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
745 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
746 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
749 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
750 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
751 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
752 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
753 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
754 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
758 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
759 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
760 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
761 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
762 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
763 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
764 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
765 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
768 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
769 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
770 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
771 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
772 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
773 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
774 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
775 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
778 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
779 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
780 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
781 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
782 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
783 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
784 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
785 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
786 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
787 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
788 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
789 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
790 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
791 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
792 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
793 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
794 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
795 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
834 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
835 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
836 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
837 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
838 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
839 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
840 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
841 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
842 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
843 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
844 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
845 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
846 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
847 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
848 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
849 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
850 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
851 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
852 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
853 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
854 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
855 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
856 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
857 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
858 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
859 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
860 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
861 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
862 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
863 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
864 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
867 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
868 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
869 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
870 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
871 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
872 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
873 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
874 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
875 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
876 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
877 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
878 MAC_AX_ERR_ASSERTION = 0x4000,
879 MAC_AX_ERR_RXI300 = 0x5000,
881 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
884 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
885 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
886 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
887 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
888 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
889 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
890 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
891 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
892 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
1052 return band == 0 ? reg_base : (reg_base + mac->band1_offset); in rtw89_mac_reg_by_idx()
1058 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); in rtw89_mac_reg_by_port()
1213 return 0; in rtw89_chip_reset_bb_rf()
1222 return 0; in rtw89_chip_reset_bb_rf()
1281 return 0; in rtw89_mac_cfg_ppdu_status_bands()
1372 return 0; in rtw89_mac_txpwr_read32()
1386 return 0; in rtw89_mac_txpwr_write32()
1400 return 0; in rtw89_mac_txpwr_write32_mask()
1463 XTAL0 = 0x0,
1464 XTAL3 = 0x3,
1465 XTAL_SI_XTAL_SC_XI = 0x04,
1466 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1467 XTAL_SI_XTAL_SC_XO = 0x05,
1468 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1469 XTAL_SI_XREF_MODE = 0x0B,
1470 XTAL_SI_PWR_CUT = 0x10,
1471 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1473 XTAL_SI_XTAL_DRV = 0x15,
1475 XTAL_SI_XTAL_PLL = 0x16,
1476 XTAL_SI_XTAL_XMD_2 = 0x24,
1478 XTAL_SI_XTAL_XMD_4 = 0x26,
1479 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1480 XTAL_SI_XREF_RF1 = 0x2D,
1481 XTAL_SI_XREF_RF2 = 0x2E,
1482 XTAL_SI_CV = 0x41,
1483 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1484 XTAL_SI_LOW_ADDR = 0x62,
1485 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1486 XTAL_SI_CTRL = 0x63,
1489 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1490 XTAL_SI_READ_VAL = 0x7A,
1491 XTAL_SI_WL_RFC_S0 = 0x80,
1492 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1493 #define XTAL_SI_RF00 BIT(0)
1494 XTAL_SI_WL_RFC_S1 = 0x81,
1495 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1496 #define XTAL_SI_RF10 BIT(0)
1497 XTAL_SI_ANAPAR_WL = 0x90,
1505 #define XTAL_SI_PON_WEI BIT(0)
1506 XTAL_SI_SRAM_CTRL = 0xA1,
1508 #define FULL_BIT_MASK GENMASK(7, 0)
1509 XTAL_SI_APBT = 0xD1,
1510 XTAL_SI_PLL = 0xE0,
1511 XTAL_SI_PLL_1 = 0xE1,