Lines Matching +full:7 +full:- +full:31
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
50 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
53 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
54 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
57 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
65 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
68 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
69 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
72 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
76 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
78 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
79 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
82 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
86 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
102 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
249 #define RTW89_DEFAULT_CQM_THOLD -70
332 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
412 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
424 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
425 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
427 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
428 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
437 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
447 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
452 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_SEC_IDX()
482 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_SEC_KEY0()
487 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_SEC_KEY1()
492 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_SEC_KEY2()
497 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_SEC_KEY3()
522 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); in RTW89_SET_EDCA_PARAM()
527 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
551 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
552 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
557 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
572 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
575 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
576 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
578 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
579 #define FW_HDR_W4_MONTH GENMASK(7, 0)
582 #define FW_HDR_W4_MIN GENMASK(31, 24)
583 #define FW_HDR_W5_YEAR GENMASK(31, 0)
588 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
597 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
598 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
603 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
605 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
624 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
627 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
628 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
630 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
631 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
634 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
636 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
683 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); in SET_CTRL_INFO_OPERATION()
779 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); in SET_CMC_TBL_AMPDU_DENSITY()
781 GENMASK(31, 28)); in SET_CMC_TBL_AMPDU_DENSITY()
835 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); in SET_CMC_TBL_RTS_RTY_LOWEST_RATE()
837 GENMASK(31, 28)); in SET_CMC_TBL_RTS_RTY_LOWEST_RATE()
856 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); in SET_CMC_TBL_MAX_AGG_NUM_SEL()
858 BIT(7)); in SET_CMC_TBL_MAX_AGG_NUM_SEL()
912 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); in SET_CMC_TBL_AMPDU_MAX_TIME()
914 GENMASK(31, 28)); in SET_CMC_TBL_AMPDU_MAX_TIME()
916 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
919 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); in SET_CMC_TBL_MAX_AGG_NUM()
921 GENMASK(7, 0)); in SET_CMC_TBL_MAX_AGG_NUM()
961 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); in SET_CMC_TBL_SECTYPE()
963 GENMASK(31, 28)); in SET_CMC_TBL_SECTYPE()
982 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); in SET_CMC_TBL_MBSSID()
984 GENMASK(7, 4)); in SET_CMC_TBL_MBSSID()
1080 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); in SET_CMC_TBL_CTRL_CNT()
1082 GENMASK(31, 28)); in SET_CMC_TBL_CTRL_CNT()
1164 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); in SET_CMC_TBL_ANTSEL_D()
1166 BIT(31)); in SET_CMC_TBL_ANTSEL_D()
1172 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); in SET_CMC_TBL_NOMINAL_PKT_PADDING_V1()
1179 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); in SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1()
1186 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); in SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1()
1193 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); in SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1()
1195 GENMASK(7, 6)); in SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1()
1198 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1201 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); in SET_CMC_TBL_ADDR_CAM_INDEX()
1203 GENMASK(7, 0)); in SET_CMC_TBL_ADDR_CAM_INDEX()
1208 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); in SET_CMC_TBL_PAID()
1215 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); in SET_CMC_TBL_ULDL()
1222 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); in SET_CMC_TBL_DOPPLER_CTRL()
1228 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); in SET_CMC_TBL_NOMINAL_PKT_PADDING()
1235 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); in SET_CMC_TBL_NOMINAL_PKT_PADDING40()
1242 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); in SET_CMC_TBL_TXPWR_TOLERENCE()
1249 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); in SET_CMC_TBL_NOMINAL_PKT_PADDING80()
1251 GENMASK(31, 30)); in SET_CMC_TBL_NOMINAL_PKT_PADDING80()
1270 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); in SET_CMC_TBL_NG()
1272 GENMASK(7, 6)); in SET_CMC_TBL_NG()
1341 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); in SET_CMC_TBL_CSI_BW()
1343 GENMASK(31, 30)); in SET_CMC_TBL_CSI_BW()
1383 #define CCTLINFO_G7_C0_OP BIT(7)
1398 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1399 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1403 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1404 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1407 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1416 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1417 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1418 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1430 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1431 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1434 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1442 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1443 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1447 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1451 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1452 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1455 #define CCTLINFO_G7_W6_ULDL BIT(31)
1456 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1459 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1466 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1467 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1475 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1482 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1483 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1495 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1498 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1499 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1507 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1514 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1549 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1552 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1553 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1558 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1562 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1569 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1571 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1573 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1575 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1577 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1580 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1584 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); in SET_FWROLE_MAINTAIN_MACID()
1618 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1630 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1640 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1651 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); in SET_GENERAL_PKT_MACID()
1666 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); in SET_GENERAL_PKT_NULL_ID()
1671 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); in SET_GENERAL_PKT_QOS_NULL_ID()
1681 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); in SET_LOG_CFG_LEVEL()
1691 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); in SET_LOG_CFG_COMP()
1696 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); in SET_LOG_CFG_COMP_EXT()
1707 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1710 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1711 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1714 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1723 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1726 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1727 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1731 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1737 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1743 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); in SET_LPS_PARM_MACID()
1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); in SET_LPS_PARM_AWAKEINTERVAL()
1819 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE()
1824 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_PKT_DROP_SEL()
1839 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); in RTW89_SET_FWCMD_PKT_DROP_PORT()
1844 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_PKT_DROP_MBSSID()
1854 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0()
1859 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1()
1864 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2()
1869 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3()
1889 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); in RTW89_SET_KEEP_ALIVE_MACID()
1919 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); in RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT()
1924 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); in RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT()
1938 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1956 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1995 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); in RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE()
2000 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); in RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID()
2010 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); in RTW89_SET_WOW_CAM_UPD_IDX()
2015 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); in RTW89_SET_WOW_CAM_UPD_WKFM1()
2020 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); in RTW89_SET_WOW_CAM_UPD_WKFM2()
2025 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); in RTW89_SET_WOW_CAM_UPD_WKFM3()
2030 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); in RTW89_SET_WOW_CAM_UPD_WKFM4()
2065 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); in RTW89_SET_WOW_CAM_UPD_VALID()
2080 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2081 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2093 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2094 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2162 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXHDR_TYPE()
2167 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXHDR_LEN()
2258 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2278 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_CONNECT_CNT()
2283 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_LINK_MODE()
2323 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); in RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR()
2368 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); in RTW89_SET_FWCMD_CXROLE_ACT_BAND()
2373 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS()
2378 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); in RTW89_SET_FWCMD_CXROLE_ACT_BW()
2383 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_ROLE()
2388 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_CH()
2413 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR()
2438 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); in RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2()
2443 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2()
2448 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); in RTW89_SET_FWCMD_CXROLE_ACT_BW_V2()
2453 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2()
2458 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_CH_V2()
2463 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2()
2468 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXROLE_MROLE_TYPE()
2473 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXROLE_MROLE_NOA()
2518 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_TXLV()
2523 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_RXLV()
2528 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_WLRSSI()
2533 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_BTRSSI()
2538 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_TXPWR()
2543 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_RXGAIN()
2548 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_BTTXPWR()
2553 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_BTRXGAIN()
2558 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_CN()
2563 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_NHM()
2568 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_BTPROFILE()
2573 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_RSVD2()
2588 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXTRX_TXTP()
2593 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXTRX_RXTP()
2598 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0)); in RTW89_SET_FWCMD_CXTRX_RXERRRA()
2613 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); in RTW89_SET_FWCMD_CXRFK_PHY_MAP()
2628 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX()
2638 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); in RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH()
2651 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2654 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2656 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2666 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2669 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2670 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2673 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2687 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2690 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2695 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2700 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2701 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2703 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2704 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2707 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2708 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2711 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2712 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2713 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2715 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2747 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2757 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2760 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2763 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2764 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2773 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2788 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2789 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2794 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2795 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2798 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2801 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2823 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2828 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2830 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2833 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2834 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2837 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2838 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2840 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2841 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2842 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2843 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2844 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2847 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2855 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2860 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_P2P_MACID()
2905 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_NOA_COUNT()
2935 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); in RTW89_SET_FWCMD_TSF32_TOGL_EARLY()
2971 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_ADD_MCC_MACID()
2986 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); in RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH()
3001 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); in RTW89_SET_FWCMD_ADD_MCC_C2H_RPT()
3051 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_ADD_MCC_DURATION()
3121 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); in RTW89_SET_FWCMD_START_MCC_MACID()
3126 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_START_MCC_TSF_LOW()
3131 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_START_MCC_TSF_HIGH()
3136 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_STOP_MCC_MACID()
3225 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); in RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET()
3265 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); in RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y()
3271 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW()
3277 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH()
3283 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X()
3289 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); in RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y()
3357 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3363 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3364 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3376 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3377 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3390 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3413 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3425 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3443 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3464 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3508 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3509 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3529 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3542 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); in RTW89_SKB_C2H_CB()
3544 return (struct rtw89_fw_c2h_attr *)skb->cb; in RTW89_SKB_C2H_CB()
3554 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3557 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3562 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3594 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3607 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3616 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3617 * HT-new: [6:5]: NA, [4:0]: MCS
3618 * For WiFi 7 chips (V1):
3619 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3623 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3630 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3634 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3648 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3651 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3653 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3656 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3659 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3661 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3671 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3687 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3693 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3695 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3697 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3699 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3704 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3708 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3710 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3730 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3740 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3748 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3750 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3797 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3811 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3818 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3820 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3826 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3872 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3940 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3941 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3995 u8 rsvd[7];
4003 u8 priv[7];
4036 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) in rtw89_compat_fw_hdr_ver_code()
4037 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); in rtw89_compat_fw_hdr_ver_code()
4039 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); in rtw89_compat_fw_hdr_ver_code()
4048 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format); in rtw89_fw_get_filename()
4063 #define H2C_HDR_CLASS GENMASK(7, 2)
4066 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4075 /* CLASS 5 - FW STATUS TEST */
4081 /* CLASS 0 - FW INFO */
4086 /* CLASS 1 - WOW */
4108 /* CLASS 2 - PS */
4124 /* CLASS 3 - FW download */
4128 /* CLASS 5 - Frame Exchange */
4138 /* CLASS 6 - Address CAM */
4142 /* CLASS 8 - Media Status Report */
4148 /* CLASS 9 - FW offload */
4184 /* CLASS 10 - Security CAM */
4188 /* CLASS 12 - BA CAM */
4194 /* CLASS 14 - MCC */
4213 /* CLASS 24 - MRC */
4234 /* CLASS 36 - AP */
4778 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_fw_h2c_init_ba_cam()
4780 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) in rtw89_fw_h2c_init_ba_cam()
4788 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_default_cmac_tbl()
4790 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); in rtw89_chip_h2c_default_cmac_tbl()
4797 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_default_dmac_tbl()
4799 if (chip->ops->h2c_default_dmac_tbl) in rtw89_chip_h2c_default_dmac_tbl()
4800 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); in rtw89_chip_h2c_default_dmac_tbl()
4808 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_update_beacon()
4810 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link); in rtw89_chip_h2c_update_beacon()
4817 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_assoc_cmac_tbl()
4819 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); in rtw89_chip_h2c_assoc_cmac_tbl()
4827 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_ampdu_link_cmac_tbl()
4829 if (chip->ops->h2c_ampdu_cmac_tbl) in rtw89_chip_h2c_ampdu_link_cmac_tbl()
4830 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link, in rtw89_chip_h2c_ampdu_link_cmac_tbl()
4846 rtwvif_link = rtwsta_link->rtwvif_link; in rtw89_chip_h2c_ampdu_cmac_tbl()
4860 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_ba_cam()
4867 rtwvif_link = rtwsta_link->rtwvif_link; in rtw89_chip_h2c_ba_cam()
4868 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link, in rtw89_chip_h2c_ba_cam()