Lines Matching +full:0 +full:x03c00000
42 (efuse->pa_type_5g & BIT(0)); in rtw8812a_read_amplifier_type()
63 BIT(1) | BIT(0)); in rtw8812a_read_amplifier_type()
72 BIT(1) | BIT(0)); in rtw8812a_read_amplifier_type()
85 if (map->rfe_option == 0xff) { in rtw8812a_read_rfe_type()
87 efuse->rfe_option = 0; in rtw8812a_read_rfe_type()
98 efuse->rfe_option = 0; in rtw8812a_read_rfe_type()
106 efuse->rfe_option = map->rfe_option & 0x3f; in rtw8812a_read_rfe_type()
110 * modify spec and notify all customer to revise the IC 0xca in rtw8812a_read_rfe_type()
117 efuse->rfe_option = 0; in rtw8812a_read_rfe_type()
128 u8 antenna = 0; in rtw88xxa_read_usb_type()
129 u8 wmode = 0; in rtw88xxa_read_usb_type()
145 for (i = 0; i < 2; i++) { in rtw88xxa_read_usb_type()
156 for (i = 0; i < 2; i++) { in rtw88xxa_read_usb_type()
195 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", in rtw88xxa_read_usb_type()
218 if (efuse->crystal_cap == 0xff) in rtw88xxa_read_efuse()
219 efuse->crystal_cap = 0x20; in rtw88xxa_read_efuse()
231 efuse->country_code[0] = map->country_code[0]; in rtw88xxa_read_efuse()
234 efuse->regd = map->rf_board_option & 0x7; in rtw88xxa_read_efuse()
235 efuse->thermal_meter[0] = map->thermal_meter; in rtw88xxa_read_efuse()
247 efuse->btcoex = (map->rf_board_option & 0xe0) == 0x20; in rtw88xxa_read_efuse()
248 efuse->share_ant = !!(efuse->bt_setting & BIT(0)); in rtw88xxa_read_efuse()
251 efuse->ant_div_cfg = 0; in rtw88xxa_read_efuse()
254 if (efuse->ant_div_type == 0xff) in rtw88xxa_read_efuse()
255 efuse->ant_div_type = 0x3; in rtw88xxa_read_efuse()
257 for (i = 0; i < 4; i++) in rtw88xxa_read_efuse()
274 return 0; in rtw88xxa_read_efuse()
288 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(0)); in rtw88xxa_reset_8051()
298 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(0)); in rtw88xxa_reset_8051()
312 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00); in rtw88xxau_hw_reset()
318 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN, BIT(0) | BIT(1)); in rtw88xxau_hw_reset()
321 rtw_write8(rtwdev, REG_RF_CTRL, 0); in rtw88xxau_hw_reset()
324 rtw_write16(rtwdev, REG_CR, 0); in rtw88xxau_hw_reset()
334 rtw_err(rtwdev, "%s: timed out waiting for 0x5[1]\n", __func__); in rtw88xxau_hw_reset()
336 /* reg0x5[0], auto FSM on */ in rtw88xxau_hw_reset()
356 rtw_write16(rtwdev, REG_CR, 0); in rtw88xxau_init_power_on()
363 if (rtw_read8(rtwdev, REG_SYS_CFG1 + 3) & BIT(0)) in rtw88xxau_init_power_on()
373 int count = 0; in rtw88xxa_llt_write()
388 return 0; in rtw88xxa_llt_write()
394 int status = 0; in rtw88xxa_llt_init()
397 for (i = 0; i < boundary - 1; i++) { in rtw88xxa_llt_init()
403 status = rtw88xxa_llt_write(rtwdev, boundary - 1, 0xFF); in rtw88xxa_llt_init()
439 pg_tbl = &chip->page_table[0]; in rtw88xxau_init_queue_reserved_page()
488 rqpn = &chip->rqpn_table[0]; in rtw88xxau_init_queue_priority()
496 txdma_pq_map = rtw_read16(rtwdev, REG_TXDMA_PQ_MAP) & 0x7; in rtw88xxau_init_queue_priority()
507 rtw_write8(rtwdev, REG_HIQ_NO_LMT_EN, 0xff); in rtw88xxau_init_queue_priority()
509 return 0; in rtw88xxau_init_queue_priority()
514 rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff); in rtw88xxa_init_wmac_setting()
515 rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400); in rtw88xxa_init_wmac_setting()
516 rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff); in rtw88xxa_init_wmac_setting()
518 rtw_write32(rtwdev, REG_MAR, 0xffffffff); in rtw88xxa_init_wmac_setting()
519 rtw_write32(rtwdev, REG_MAR + 4, 0xffffffff); in rtw88xxa_init_wmac_setting()
524 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xffff1); in rtw88xxa_init_adaptive_ctrl()
525 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030); in rtw88xxa_init_adaptive_ctrl()
530 rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a); in rtw88xxa_init_edca()
531 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a); in rtw88xxa_init_edca()
533 rtw_write16(rtwdev, REG_SIFS, 0x100a); in rtw88xxa_init_edca()
534 rtw_write16(rtwdev, REG_SIFS + 2, 0x100a); in rtw88xxa_init_edca()
536 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); in rtw88xxa_init_edca()
537 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); in rtw88xxa_init_edca()
538 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); in rtw88xxa_init_edca()
539 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); in rtw88xxa_init_edca()
541 rtw_write8(rtwdev, REG_USTIME_TSF, 0x50); in rtw88xxa_init_edca()
542 rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50); in rtw88xxa_init_edca()
549 rtw_write32_mask(rtwdev, REG_DWBCN0_CTRL, 0xf0, in rtw88xxau_tx_aggregation()
566 rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME); in rtw88xxa_init_beacon_parameters()
567 rtw_write8(rtwdev, REG_DRVERLYINT, 0x05); in rtw88xxa_init_beacon_parameters()
569 rtw_write16(rtwdev, REG_BCNTCFG, 0x4413); in rtw88xxa_init_beacon_parameters()
593 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw88xxa_phy_bb_config()
595 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x7FF80000, in rtw88xxa_phy_bb_config()
598 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x00FFF000, in rtw88xxa_phy_bb_config()
606 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) in rtw88xxa_phy_rf_config()
613 rtw_write32_mask(rtwdev, REG_RXPSEL, 0xff, 0x11); in rtw8812a_config_1t()
616 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKLWORD, 0x1111); in rtw8812a_config_1t()
619 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0c000000, 0x0); in rtw8812a_config_1t()
622 rtw_write32_mask(rtwdev, REG_RX_MCS_LIMIT, 0xc0000060, 0x4); in rtw8812a_config_1t()
625 rtw_write32_mask(rtwdev, REG_3WIRE_SWB, 0xf, 0x4); in rtw8812a_config_1t()
628 rtw_write32_mask(rtwdev, REG_LSSI_WRITE_B, MASKDWORD, 0); in rtw8812a_config_1t()
631 rtw_write32_mask(rtwdev, REG_AFE_PWR1_B, MASKDWORD, 0); in rtw8812a_config_1t()
632 rtw_write32_mask(rtwdev, REG_AFE_PWR2_B, MASKDWORD, 0); in rtw8812a_config_1t()
636 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
637 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
638 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
639 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
644 static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; in rtw88xxa_get_bb_swing()
655 tx_bb_swing &= 0x3; in rtw88xxa_get_bb_swing()
668 for (i = 0; i < ARRAY_SIZE(rtw88xxa_txscale_tbl); i++) { in rtw88xxa_get_swing_index()
685 dm_info->default_cck_index = 0; in rtw88xxa_pwrtrack_init()
691 dm_info->delta_power_index[path] = 0; in rtw88xxa_pwrtrack_init()
692 dm_info->delta_power_index_last[path] = 0; in rtw88xxa_pwrtrack_init()
711 if (reg_cr == 0 || reg_cr == 0xEA) in rtw88xxa_power_off()
719 /* set Reg 0xf008[3:4] to 2'11 to enable U1/U2 Mode in USB3.0. */ in rtw88xxa_power_off()
721 rtw_write8_set(rtwdev, REG_USB_MOD, 0x18); in rtw88xxa_power_off()
723 rtw_write32(rtwdev, REG_HISR0, 0xffffffff); in rtw88xxa_power_off()
724 rtw_write32(rtwdev, REG_HISR1, 0xffffffff); in rtw88xxa_power_off()
725 rtw_write32(rtwdev, REG_HIMR0, 0); in rtw88xxa_power_off()
726 rtw_write32(rtwdev, REG_HIMR1, 0); in rtw88xxa_power_off()
738 rtw_write8(rtwdev, REG_CR, 0); in rtw88xxa_power_off()
746 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0); in rtw88xxa_power_off()
768 rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN, 0); in rtw8821a_set_ext_band_switch()
770 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf, 7); in rtw8821a_set_ext_band_switch()
771 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf0, 7); in rtw8821a_set_ext_band_switch()
785 /* 0xCB0[15:12] = 0x7 (LNA_On)*/ in rtw8821a_phy_set_rfe_reg_24g()
786 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x7); in rtw8821a_phy_set_rfe_reg_24g()
787 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/ in rtw8821a_phy_set_rfe_reg_24g()
788 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x7); in rtw8821a_phy_set_rfe_reg_24g()
793 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0); in rtw8821a_phy_set_rfe_reg_24g()
794 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x2); in rtw8821a_phy_set_rfe_reg_24g()
795 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x2); in rtw8821a_phy_set_rfe_reg_24g()
798 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0); in rtw8821a_phy_set_rfe_reg_24g()
799 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0); in rtw8821a_phy_set_rfe_reg_24g()
800 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7); in rtw8821a_phy_set_rfe_reg_24g()
801 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7); in rtw8821a_phy_set_rfe_reg_24g()
809 /* 0xCB0[15:12] = 0x7 (LNA_On)*/ in rtw8821a_phy_set_rfe_reg_5g()
810 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x5); in rtw8821a_phy_set_rfe_reg_5g()
811 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/ in rtw8821a_phy_set_rfe_reg_5g()
812 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x4); in rtw8821a_phy_set_rfe_reg_5g()
815 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0); in rtw8821a_phy_set_rfe_reg_5g()
816 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0); in rtw8821a_phy_set_rfe_reg_5g()
817 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7); in rtw8821a_phy_set_rfe_reg_5g()
818 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7); in rtw8821a_phy_set_rfe_reg_5g()
824 case 0: in rtw8812a_phy_set_rfe_reg_24g()
826 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
827 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
828 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
829 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
833 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x777777); in rtw8812a_phy_set_rfe_reg_24g()
834 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
835 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
836 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
838 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
839 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
840 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
841 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
845 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337770); in rtw8812a_phy_set_rfe_reg_24g()
846 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337770); in rtw8812a_phy_set_rfe_reg_24g()
847 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_24g()
848 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_24g()
849 rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1); in rtw8812a_phy_set_rfe_reg_24g()
852 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
853 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
854 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x001); in rtw8812a_phy_set_rfe_reg_24g()
855 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x001); in rtw8812a_phy_set_rfe_reg_24g()
858 rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x77); in rtw8812a_phy_set_rfe_reg_24g()
859 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); in rtw8812a_phy_set_rfe_reg_24g()
860 rtw_write8_clr(rtwdev, REG_RFE_INV_A + 3, BIT(0)); in rtw8812a_phy_set_rfe_reg_24g()
861 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_24g()
864 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07772770); in rtw8812a_phy_set_rfe_reg_24g()
865 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07772770); in rtw8812a_phy_set_rfe_reg_24g()
866 rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077); in rtw8812a_phy_set_rfe_reg_24g()
867 rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077); in rtw8812a_phy_set_rfe_reg_24g()
877 case 0: in rtw8812a_phy_set_rfe_reg_5g()
878 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717); in rtw8812a_phy_set_rfe_reg_5g()
879 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717); in rtw8812a_phy_set_rfe_reg_5g()
880 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
881 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
885 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x337717); in rtw8812a_phy_set_rfe_reg_5g()
886 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717); in rtw8812a_phy_set_rfe_reg_5g()
887 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000); in rtw8812a_phy_set_rfe_reg_5g()
888 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_5g()
890 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717); in rtw8812a_phy_set_rfe_reg_5g()
891 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717); in rtw8812a_phy_set_rfe_reg_5g()
892 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_5g()
893 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000); in rtw8812a_phy_set_rfe_reg_5g()
898 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337777); in rtw8812a_phy_set_rfe_reg_5g()
899 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777); in rtw8812a_phy_set_rfe_reg_5g()
900 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
901 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
904 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337717); in rtw8812a_phy_set_rfe_reg_5g()
905 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337717); in rtw8812a_phy_set_rfe_reg_5g()
906 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
907 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
908 rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1); in rtw8812a_phy_set_rfe_reg_5g()
911 rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x33); in rtw8812a_phy_set_rfe_reg_5g()
912 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777); in rtw8812a_phy_set_rfe_reg_5g()
913 rtw_write8_set(rtwdev, REG_RFE_INV_A + 3, BIT(0)); in rtw8812a_phy_set_rfe_reg_5g()
914 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010); in rtw8812a_phy_set_rfe_reg_5g()
917 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07737717); in rtw8812a_phy_set_rfe_reg_5g()
918 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07737717); in rtw8812a_phy_set_rfe_reg_5g()
919 rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077); in rtw8812a_phy_set_rfe_reg_5g()
920 rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077); in rtw8812a_phy_set_rfe_reg_5g()
936 rtwdev->efuse.ant_div_cfg == 0) in rtw88xxa_switch_band()
945 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0); in rtw88xxa_switch_band()
947 rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x1); in rtw88xxa_switch_band()
948 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x17); in rtw88xxa_switch_band()
953 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x02); in rtw88xxa_switch_band()
955 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04); in rtw88xxa_switch_band()
957 rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 0); in rtw88xxa_switch_band()
962 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x1); in rtw88xxa_switch_band()
963 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x1); in rtw88xxa_switch_band()
969 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates); in rtw88xxa_switch_band()
978 read_poll_timeout_atomic(rtw_read16, reg_41a, (reg_41a & 0x30) == 0x30, in rtw88xxa_switch_band()
984 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 1); in rtw88xxa_switch_band()
986 rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x2); in rtw88xxa_switch_band()
987 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x15); in rtw88xxa_switch_band()
988 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04); in rtw88xxa_switch_band()
990 rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 1); in rtw88xxa_switch_band()
995 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0); in rtw88xxa_switch_band()
996 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf); in rtw88xxa_switch_band()
1000 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates); in rtw88xxa_switch_band()
1015 return 0; in rtw88xxa_power_on()
1081 rtw_write8(rtwdev, REG_HMETFR, 0xf); in rtw88xxa_power_on()
1099 rtw_write32(rtwdev, REG_HIMR0, 0); in rtw88xxa_power_on()
1100 rtw_write32(rtwdev, REG_HIMR1, 0); in rtw88xxa_power_on()
1102 rtw_write32_mask(rtwdev, REG_CR, 0x30000, 0x2); in rtw88xxa_power_on()
1109 rtw_write8(rtwdev, REG_ACKTO, 0x80); in rtw88xxa_power_on()
1114 rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xff); in rtw88xxa_power_on()
1119 rtw_write8(rtwdev, REG_USB3_RXITV, 0x01); in rtw88xxa_power_on()
1121 /* burst length=4, set 0x3400 for burst length=2 */ in rtw88xxa_power_on()
1122 rtw_write16(rtwdev, REG_RXDMA_STATUS, 0x7400); in rtw88xxa_power_on()
1123 rtw_write8(rtwdev, REG_RXDMA_STATUS + 1, 0xf5); in rtw88xxa_power_on()
1125 /* 0x456 = 0x70, sugguested by Zhilin */ in rtw88xxa_power_on()
1127 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, 0x5e); in rtw88xxa_power_on()
1129 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, 0x70); in rtw88xxa_power_on()
1131 rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, 0xffffffff); in rtw88xxa_power_on()
1132 rtw_write8(rtwdev, REG_USTIME_TSF, 0x50); in rtw88xxa_power_on()
1133 rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50); in rtw88xxa_power_on()
1136 /* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */ in rtw88xxa_power_on()
1142 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, 0x18); in rtw88xxa_power_on()
1144 rtw_write8(rtwdev, REG_PIFS, 0x00); in rtw88xxa_power_on()
1147 /* 0x0a0a too small, it can't pass AC logo. change to 0x1f1f */ in rtw88xxa_power_on()
1148 rtw_write16(rtwdev, REG_MAX_AGGR_NUM, 0x1f1f); in rtw88xxa_power_on()
1149 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, 0x80); in rtw88xxa_power_on()
1150 rtw_write32(rtwdev, REG_FAST_EDCA_CTRL, 0x03087777); in rtw88xxa_power_on()
1152 rtw_write16(rtwdev, REG_MAX_AGGR_NUM, 0x1f1f); in rtw88xxa_power_on()
1160 rtw_write32(rtwdev, REG_ARFR0, 0x00000010); in rtw88xxa_power_on()
1161 rtw_write32(rtwdev, REG_ARFRH0, 0xfffff000); in rtw88xxa_power_on()
1164 rtw_write32(rtwdev, REG_ARFR1_V1, 0x00000010); in rtw88xxa_power_on()
1165 rtw_write32(rtwdev, REG_ARFRH1_V1, 0x003ff000); in rtw88xxa_power_on()
1168 rtw_write32(rtwdev, REG_ARFR2_V1, 0x00000015); in rtw88xxa_power_on()
1169 rtw_write32(rtwdev, REG_ARFRH2_V1, 0x003ff000); in rtw88xxa_power_on()
1172 rtw_write32(rtwdev, REG_ARFR3_V1, 0x00000015); in rtw88xxa_power_on()
1173 rtw_write32(rtwdev, REG_ARFRH3_V1, 0xffcff000); in rtw88xxa_power_on()
1187 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xff); in rtw88xxa_power_on()
1188 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff); in rtw88xxa_power_on()
1189 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0); in rtw88xxa_power_on()
1197 /* 0x4c6[3] 1: RTS BW = Data BW in rtw88xxa_power_on()
1198 * 0: RTS BW depends on CCA / secondary CCA result. in rtw88xxa_power_on()
1203 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x0f); in rtw88xxa_power_on()
1206 rtw_write8(rtwdev, REG_EARLY_MODE_CONTROL + 3, 0x01); in rtw88xxa_power_on()
1208 rtw_write16(rtwdev, REG_TX_RPT_TIME, 0x3df0); in rtw88xxa_power_on()
1211 rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0); in rtw88xxa_power_on()
1212 rtw_write8(rtwdev, REG_ACLK_MON, 0x0); in rtw88xxa_power_on()
1214 rtw_write8(rtwdev, REG_USB_HRPWM, 0); in rtw88xxa_power_on()
1235 return 0; in rtw88xxa_power_on()
1264 * Toggling CCA would affect RF 0x0, skip it. in rtw88xxa_phy_read_rf()
1266 set_cca = addr != 0x0 && chip->id == RTW_CHIP_TYPE_8812A && in rtw88xxa_phy_read_rf()
1272 addr &= 0xff; in rtw88xxa_phy_read_rf()
1274 pi_mode = rtw_read32_mask(rtwdev, pi_addr[rf_path], 0x4); in rtw88xxa_phy_read_rf()
1297 rtw_write32_mask(rtwdev, REG_ADCCLK, 0xC00, 0x3); in rtw8812a_phy_fix_spur()
1299 rtw_write32_mask(rtwdev, REG_ADCCLK, 0xC00, 0x2); in rtw8812a_phy_fix_spur()
1305 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x3); in rtw8812a_phy_fix_spur()
1310 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x2); in rtw8812a_phy_fix_spur()
1311 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0); in rtw8812a_phy_fix_spur()
1318 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x3); in rtw8812a_phy_fix_spur()
1320 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x2); in rtw8812a_phy_fix_spur()
1332 fc_area = 0x494; in rtw88xxa_switch_channel()
1335 fc_area = 0x453; in rtw88xxa_switch_channel()
1338 fc_area = 0x452; in rtw88xxa_switch_channel()
1342 fc_area = 0x412; in rtw88xxa_switch_channel()
1344 fc_area = 0x96a; in rtw88xxa_switch_channel()
1348 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area); in rtw88xxa_switch_channel()
1350 for (path = 0; path < hal->rf_path_num; path++) { in rtw88xxa_switch_channel()
1353 rf_mod_ag = 0x101; in rtw88xxa_switch_channel()
1356 rf_mod_ag = 0x301; in rtw88xxa_switch_channel()
1360 rf_mod_ag = 0x501; in rtw88xxa_switch_channel()
1362 rf_mod_ag = 0x000; in rtw88xxa_switch_channel()
1393 u8 txsc40 = 0, txsc20, txsc; in rtw88xxa_post_set_bw_mode()
1414 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300200); in rtw88xxa_post_set_bw_mode()
1415 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0); in rtw88xxa_post_set_bw_mode()
1418 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, 7); in rtw88xxa_post_set_bw_mode()
1420 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, 8); in rtw88xxa_post_set_bw_mode()
1424 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300201); in rtw88xxa_post_set_bw_mode()
1425 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0); in rtw88xxa_post_set_bw_mode()
1426 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3C, txsc); in rtw88xxa_post_set_bw_mode()
1427 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0000000, txsc); in rtw88xxa_post_set_bw_mode()
1438 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, l1pkval); in rtw88xxa_post_set_bw_mode()
1447 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300202); in rtw88xxa_post_set_bw_mode()
1449 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3C, txsc); in rtw88xxa_post_set_bw_mode()
1450 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0000000, txsc); in rtw88xxa_post_set_bw_mode()
1461 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, l1pkval); in rtw88xxa_post_set_bw_mode()
1483 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0); in rtw88xxa_set_channel_rf()
1578 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw88xxa_set_tx_power_index_by_rate()
1583 shift = rate & 0x3; in rtw88xxa_set_tx_power_index_by_rate()
1594 if (shift == 0x3 || write_1ss_mcs9) { in rtw88xxa_set_tx_power_index_by_rate()
1595 rate_idx = rate & 0xfc; in rtw88xxa_set_tx_power_index_by_rate()
1597 rate_idx -= 0x10; in rtw88xxa_set_tx_power_index_by_rate()
1602 *phy_pwr_idx = 0; in rtw88xxa_set_tx_power_index_by_rate()
1617 write_data = 0; in rtw88xxa_tx_power_training()
1619 for (i = 0; i < 3; i++) { in rtw88xxa_tx_power_training()
1620 if (i == 0) in rtw88xxa_tx_power_training()
1630 rtw_write32_mask(rtwdev, write_offset[path], 0xffffff, write_data); in rtw88xxa_tx_power_training()
1636 u32 phy_pwr_idx = 0; in rtw88xxa_set_tx_power_index()
1639 for (path = 0; path < hal->rf_path_num; path++) { in rtw88xxa_set_tx_power_index()
1640 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { in rtw88xxa_set_tx_power_index()
1710 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw88xxa_false_alarm_statistics()
1711 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw88xxa_false_alarm_statistics()
1722 /* [31] = 0 --> Page C */ in rtw88xxa_iqk_backup_mac_bb()
1723 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); in rtw88xxa_iqk_backup_mac_bb()
1726 for (i = 0; i < macbb_num; i++) in rtw88xxa_iqk_backup_mac_bb()
1736 /* [31] = 0 --> Page C */ in rtw88xxa_iqk_backup_afe()
1737 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); in rtw88xxa_iqk_backup_afe()
1740 for (i = 0; i < afe_num; i++) in rtw88xxa_iqk_backup_afe()
1752 /* [31] = 0 --> Page C */ in rtw88xxa_iqk_restore_mac_bb()
1753 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); in rtw88xxa_iqk_restore_mac_bb()
1756 for (i = 0; i < macbb_num; i++) in rtw88xxa_iqk_restore_mac_bb()
1763 /* [31] = 0 --> Page C */ in rtw88xxa_iqk_configure_mac()
1764 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); in rtw88xxa_iqk_configure_mac()
1766 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f); in rtw88xxa_iqk_configure_mac()
1768 (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION, 0x0); in rtw88xxa_iqk_configure_mac()
1771 rtw_write8(rtwdev, REG_RXPSEL, 0x00); in rtw88xxa_iqk_configure_mac()
1774 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xc); in rtw88xxa_iqk_configure_mac()
1777 rtw_write8(rtwdev, REG_CCK_RX + 3, 0xf); in rtw88xxa_iqk_configure_mac()
1788 for (i = 0; i < average; i++) { in rtw88xxa_iqk_finish()
1870 } else if (ofdm_swing_idx == 0) { in rtw88xxa_pwrtrack_set()
1876 dm_info->txagc_remnant_cck = 0; in rtw88xxa_pwrtrack_set()
1877 dm_info->txagc_remnant_ofdm[path] = 0; in rtw88xxa_pwrtrack_set()
1897 if (rtwdev->efuse.thermal_meter[0] == 0xff) { in rtw88xxa_phy_pwrtrack()
1898 pr_err_once("efuse thermal meter is 0xff\n"); in rtw88xxa_phy_pwrtrack()
1902 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw88xxa_phy_pwrtrack()
1951 static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed}; in rtw88xxa_phy_cck_pd_set()