93 	{.bitrate = 10, .hw_value = 0x00,},
94 	{.bitrate = 20, .hw_value = 0x01,},
95 	{.bitrate = 55, .hw_value = 0x02,},
96 	{.bitrate = 110, .hw_value = 0x03,},
97 	{.bitrate = 60, .hw_value = 0x04,},
98 	{.bitrate = 90, .hw_value = 0x05,},
99 	{.bitrate = 120, .hw_value = 0x06,},
100 	{.bitrate = 180, .hw_value = 0x07,},
101 	{.bitrate = 240, .hw_value = 0x08,},
102 	{.bitrate = 360, .hw_value = 0x09,},
103 	{.bitrate = 480, .hw_value = 0x0a,},
104 	{.bitrate = 540, .hw_value = 0x0b,},
132 		return 0;  in rtw_desc_to_bitrate()
148 	.ht_cap = {0},
149 	.vht_cap = {0},
162 	.ht_cap = {0},
163 	.vht_cap = {0},
174 	u8 fix_rate_enable = 0;  in rtw_dynamic_csi_rate()
200 	rtwvif->stats.tx_unicast = 0;  in rtw_vif_watch_dog_iter()
201 	rtwvif->stats.rx_unicast = 0;  in rtw_vif_watch_dog_iter()
202 	rtwvif->stats.tx_cnt = 0;  in rtw_vif_watch_dog_iter()
203 	rtwvif->stats.rx_cnt = 0;  in rtw_vif_watch_dog_iter()
249 		rtw_coex_wl_status_change_notify(rtwdev, 0);  in rtw_watch_dog_work()
266 	stats->tx_unicast = 0;  in rtw_watch_dog_work()
267 	stats->rx_unicast = 0;  in rtw_watch_dog_work()
268 	stats->tx_cnt = 0;  in rtw_watch_dog_work()
269 	stats->rx_cnt = 0;  in rtw_watch_dog_work()
365 	for (i = 0; i < ARRAY_SIZE(sta->txq); i++)  in rtw_sta_add()
377 	return 0;  in rtw_sta_add()
394 	for (i = 0; i < ARRAY_SIZE(sta->txq); i++)  in rtw_sta_remove()
422 		for (i = 0; i < segs->num; i++)  in rtw_fwcd_prep()
433 	return 0;  in rtw_fwcd_prep()
456 	hdr->padding1 = 0x01234567;  in rtw_fwcd_next()
457 	hdr->padding2 = 0x89abcdef;  in rtw_fwcd_next()
500 	if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {  in rtw_fw_dump_crash_log()
505 	if (GET_FW_DUMP_LEN(buf) == 0) {  in rtw_fw_dump_crash_log()
506 		rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");  in rtw_fw_dump_crash_log()
511 	if (seq > 0) {  in rtw_fw_dump_crash_log()
517 	return 0;  in rtw_fw_dump_crash_log()
524 	u32 dump_size, done_size = 0;  in rtw_dump_fw()
539 				"ddma fw 0x%x [+0x%x] to fw fifo fail\n",  in rtw_dump_fw()
544 		ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,  in rtw_dump_fw()
548 				"dump fw 0x%x [+0x%x] from fw fifo fail\n",  in rtw_dump_fw()
557 	return 0;  in rtw_dump_fw()
566 	if (addr & 0x3) {  in rtw_dump_reg()
567 		WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);  in rtw_dump_reg()
575 	for (i = 0; i < size; i += 4)  in rtw_dump_reg()
578 	return 0;  in rtw_dump_reg()
594 		rtwvif->aid = 0;  in rtw_vif_assoc_changed()
615 	if (rtwdev->sta_cnt == 0) {  in rtw_reset_sta_iter()
616 		rtw_warn(rtwdev, "sta count before reset should not be 0\n");  in rtw_reset_sta_iter()
642 	int ret = 0;  in __fw_recovery_work()
660 	rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);  in __fw_recovery_work()
697 		ret = ieee80211_start_tx_ba_session(sta, tid, 0);  in rtw_txq_ba_iter()
861 		center_chan = 0;  in rtw_get_channel_params()
879 	if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))  in rtw_set_channel()
928 	for (i = 0; i < ETH_ALEN; i++)  in rtw_vif_write_addr()
965 	u8 bw = 0;  in hw_bw_cap_to_bitamp()
1009 	u64 ra_mask = 0;  in get_vht_ra_mask()
1015 	for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {  in get_vht_ra_mask()
1016 		vht_mcs_cap = mcs_map & 0x3;  in get_vht_ra_mask()
1019 			ra_mask |= 0x3ffULL << nss;  in get_vht_ra_mask()
1022 			ra_mask |= 0x1ffULL << nss;  in get_vht_ra_mask()
1024 		case 0: /* MCS7 */  in get_vht_ra_mask()
1025 			ra_mask |= 0x0ffULL << nss;  in get_vht_ra_mask()
1037 	u8 rate_id = 0;  in get_rate_id()
1116 #define RA_MASK_CCK_RATES	0x0000f
1117 #define RA_MASK_OFDM_RATES	0x00ff0
1118 #define RA_MASK_HT_RATES_1SS	(0xff000ULL << 0)
1119 #define RA_MASK_HT_RATES_2SS	(0xff000ULL << 8)
1120 #define RA_MASK_HT_RATES_3SS	(0xff000ULL << 16)
1124 #define RA_MASK_VHT_RATES_1SS	(0x3ff000ULL << 0)
1125 #define RA_MASK_VHT_RATES_2SS	(0x3ff000ULL << 10)
1126 #define RA_MASK_VHT_RATES_3SS	(0x3ff000ULL << 20)
1130 #define RA_MASK_CCK_IN_BG	0x00005
1131 #define RA_MASK_CCK_IN_HT	0x00005
1132 #define RA_MASK_CCK_IN_VHT	0x00005
1133 #define RA_MASK_OFDM_IN_VHT	0x00010
1134 #define RA_MASK_OFDM_IN_HT_2G	0x00010
1135 #define RA_MASK_OFDM_IN_HT_5G	0x00030
1142 		return 0xffffffffffffffffULL;  in rtw_rate_mask_rssi()
1144 	if (rssi_level == 0)  in rtw_rate_mask_rssi()
1145 		return 0xffffffffffffffffULL;  in rtw_rate_mask_rssi()
1147 		return 0xfffffffffffffff0ULL;  in rtw_rate_mask_rssi()
1149 		return 0xffffffffffffefe0ULL;  in rtw_rate_mask_rssi()
1151 		return 0xffffffffffffcfc0ULL;  in rtw_rate_mask_rssi()
1153 		return 0xffffffffffff8f80ULL;  in rtw_rate_mask_rssi()
1155 		return 0xffffffffffff0f00ULL;  in rtw_rate_mask_rssi()
1160 	if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)  in rtw_rate_mask_recover()
1163 	if (ra_mask == 0)  in rtw_rate_mask_recover()
1174 	u64 cfg_mask = GENMASK_ULL(63, 0);  in rtw_rate_mask_cfg()
1192 			cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],  in rtw_rate_mask_cfg()
1199 			cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],  in rtw_rate_mask_cfg()
1221 	u8 stbc_en = 0;  in rtw_update_sta_info()
1222 	u8 ldpc_en = 0;  in rtw_update_sta_info()
1224 	u64 ra_mask = 0;  in rtw_update_sta_info()
1225 	u64 ra_mask_bak = 0;  in rtw_update_sta_info()
1238 			   (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);  in rtw_update_sta_info()
1274 		} else if (sta->deflink.supp_rates[0] <= 0xf) {  in rtw_update_sta_info()
1284 		wireless_set = 0;  in rtw_update_sta_info()
1305 	if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000)  in rtw_update_sta_info()
1307 	else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000)  in rtw_update_sta_info()
1331 	int ret = 0;  in rtw_wait_firmware_completion()
1424 	return 0;  in rtw_power_on()
1453 	u32 config = 0;  in rtw_core_scan_start()
1454 	int ret = 0;  in rtw_core_scan_start()
1481 	u32 config = 0;  in rtw_core_scan_complete()
1522 	return 0;  in rtw_core_start()
1566 	ht_cap->cap = 0;  in rtw_init_ht_cap()
1584 		ht_cap->mcs.rx_mask[0] = 0xFF;  in rtw_init_ht_cap()
1585 		ht_cap->mcs.rx_mask[1] = 0xFF;  in rtw_init_ht_cap()
1586 		ht_cap->mcs.rx_mask[4] = 0x01;  in rtw_init_ht_cap()
1589 		ht_cap->mcs.rx_mask[0] = 0xFF;  in rtw_init_ht_cap()
1590 		ht_cap->mcs.rx_mask[1] = 0x00;  in rtw_init_ht_cap()
1591 		ht_cap->mcs.rx_mask[4] = 0x01;  in rtw_init_ht_cap()
1613 		       0;  in rtw_init_vht_cap()
1624 	mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |  in rtw_init_vht_cap()
1708 		ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);  in rtw_vif_smps_iter()
1710 		ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);  in rtw_vif_smps_iter()
1738 	fw->feature = feature & FW_FEATURE_SIG ? feature : 0;  in __update_firmware_feature()
1765 	fw->h2c_version = 0;  in __update_firmware_info_legacy()
1833 	return 0;  in rtw_load_firmware()
1844 		rtwdev->hci.rpwm_addr = 0x03d9;  in rtw_chip_parameter_setup()
1845 		rtwdev->hci.cpwm_addr = 0x03da;  in rtw_chip_parameter_setup()
1852 		rtwdev->hci.rpwm_addr = 0xfe58;  in rtw_chip_parameter_setup()
1853 		rtwdev->hci.cpwm_addr = 0xfe57;  in rtw_chip_parameter_setup()
1862 	hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;  in rtw_chip_parameter_setup()
1886 	return 0;  in rtw_chip_parameter_setup()
1921 	return 0;  in rtw_chip_efuse_enable()
1939 		return 0;  in rtw_dump_hw_feature()
1947 	for (i = 0; i < HW_FEATURE_LEN; i++)  in rtw_dump_hw_feature()
1950 	rtw_write8(rtwdev, REG_C2HEVT, 0);  in rtw_dump_hw_feature()
1966 		"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",  in rtw_dump_hw_feature()
1970 	return 0;  in rtw_dump_hw_feature()
2003 	if (efuse->crystal_cap == 0xff)  in rtw_chip_efuse_info_setup()
2004 		efuse->crystal_cap = 0;  in rtw_chip_efuse_info_setup()
2005 	if (efuse->pa_type_2g == 0xff)  in rtw_chip_efuse_info_setup()
2006 		efuse->pa_type_2g = 0;  in rtw_chip_efuse_info_setup()
2007 	if (efuse->pa_type_5g == 0xff)  in rtw_chip_efuse_info_setup()
2008 		efuse->pa_type_5g = 0;  in rtw_chip_efuse_info_setup()
2009 	if (efuse->lna_type_2g == 0xff)  in rtw_chip_efuse_info_setup()
2010 		efuse->lna_type_2g = 0;  in rtw_chip_efuse_info_setup()
2011 	if (efuse->lna_type_5g == 0xff)  in rtw_chip_efuse_info_setup()
2012 		efuse->lna_type_5g = 0;  in rtw_chip_efuse_info_setup()
2013 	if (efuse->channel_plan == 0xff)  in rtw_chip_efuse_info_setup()
2014 		efuse->channel_plan = 0x7f;  in rtw_chip_efuse_info_setup()
2015 	if (efuse->rf_board_option == 0xff)  in rtw_chip_efuse_info_setup()
2016 		efuse->rf_board_option = 0;  in rtw_chip_efuse_info_setup()
2017 	if (efuse->bt_setting & BIT(0))  in rtw_chip_efuse_info_setup()
2019 	if (efuse->regd == 0xff)  in rtw_chip_efuse_info_setup()
2020 		efuse->regd = 0;  in rtw_chip_efuse_info_setup()
2021 	if (efuse->tx_bb_swing_setting_2g == 0xff)  in rtw_chip_efuse_info_setup()
2022 		efuse->tx_bb_swing_setting_2g = 0;  in rtw_chip_efuse_info_setup()
2023 	if (efuse->tx_bb_swing_setting_5g == 0xff)  in rtw_chip_efuse_info_setup()
2024 		efuse->tx_bb_swing_setting_5g = 0;  in rtw_chip_efuse_info_setup()
2026 	efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;  in rtw_chip_efuse_info_setup()
2027 	efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;  in rtw_chip_efuse_info_setup()
2028 	efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;  in rtw_chip_efuse_info_setup()
2029 	efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;  in rtw_chip_efuse_info_setup()
2030 	efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0;  in rtw_chip_efuse_info_setup()
2061 	return 0;  in rtw_chip_board_info_setup()
2086 	return 0;  in rtw_chip_info_setup()
2102 	for (i = 0; i < RTW_EVM_NUM; i++)  in rtw_stats_init()
2104 	for (i = 0; i < RTW_SNR_NUM; i++)  in rtw_stats_init()
2118 		    rtw_tx_report_purge_timer, 0);  in rtw_core_init()
2119 	rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);  in rtw_core_init()
2183 	return 0;  in rtw_core_init()
2229 	int max_tx_headroom = 0;  in rtw_register_hw()
2312 	rtwdev->bf_info.bfer_mu_cnt = 0;  in rtw_register_hw()
2313 	rtwdev->bf_info.bfer_su_cnt = 0;  in rtw_register_hw()
2315 	return 0;  in rtw_register_hw()
2340 	for (i = 0; i < nbytes; i++) {  in rtw_swap_reg_nbytes()