Lines Matching defs:rtl_phy

1284 struct rtl_phy {  struct
1285 	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
1286 	struct init_gain initgain_backup;
1287 	enum io_type current_io_type;
1289 	u8 rf_mode;
1290 	u8 rf_type;
1291 	u8 current_chan_bw;
1292 	u8 set_bwmode_inprogress;
1293 	u8 sw_chnl_inprogress;
1294 	u8 sw_chnl_stage;
1295 	u8 sw_chnl_step;
1296 	u8 current_channel;
1297 	u8 set_io_inprogress;
1298 	u8 lck_inprogress;
1301 	s32 reg_e94;
1302 	s32 reg_e9c;
1303 	s32 reg_ea4;
1304 	s32 reg_eac;
1305 	s32 reg_eb4;
1306 	s32 reg_ebc;
1307 	s32 reg_ec4;
1308 	s32 reg_ecc;
1309 	u32 reg_c04, reg_c08, reg_874;
1310 	u32 adda_backup[16];
1311 	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1312 	u32 iqk_bb_backup[10];
1313 	bool iqk_initialized;
1315 	bool rfpath_rx_enable[MAX_RF_PATH];
1316 	u8 reg_837;
1318 	bool need_iqk;
1319 	struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1321 	bool rfpi_enable;
1323 	u8 pwrgroup_cnt;
1324 	u8 cck_high_power;
1326 	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1328 	u32 mcs_offset[MAX_PG_GROUP][16];
1329 	u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1333 	u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1336 	u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1339 	u8 default_initialgain[4];
1342 	u8 cur_cck_txpwridx;
1343 	u8 cur_ofdm24g_txpwridx;
1344 	u8 cur_bw20_txpwridx;
1345 	u8 cur_bw40_txpwridx;
1347 	s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1352 	s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1358 	u32 rfreg_chnlval[2];
1359 	u32 reg_rf3c[2];	/* pathA / pathB  */
1361 	u32 backup_rf_0x1a;/*92ee*/
1363 	u8 framesync;
1364 	u32 framesync_c34;
1366 	u8 num_total_rfpath;
1367 	struct phy_parameters hwparam_tables[MAX_TAB];
1368 	u16 rf_pathmap;
1370 	enum rt_polarity_ctl polarity_ctl;