Lines Matching +full:0 +full:xe14

20 	u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;  in _rtl92s_get_powerbase()
23 for (i = 0; i < 2; i++) in _rtl92s_get_powerbase()
28 pwrbase0 = pwrlevel[0] + (rtlefuse->legacy_ht_txpowerdiff & 0xf); in _rtl92s_get_powerbase()
37 pwrbase0 = pwrlevel[0] + legacy_pwrdiff; in _rtl92s_get_powerbase()
48 for (i = 0; i < 2; i++) { in _rtl92s_get_powerbase()
54 if (ht20_pwrdiff < 8) /* 0~+7 */ in _rtl92s_get_powerbase()
63 pwrbase1 = pwrlevel[0]; in _rtl92s_get_powerbase()
70 p_final_pwridx[0] = pwrlevel[0]; in _rtl92s_get_powerbase()
78 p_final_pwridx[0] += rtlefuse->pwrgroup_ht40 in _rtl92s_get_powerbase()
85 p_final_pwridx[0] += rtlefuse->pwrgroup_ht20 in _rtl92s_get_powerbase()
99 "40MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n", in _rtl92s_get_powerbase()
100 p_final_pwridx[0], p_final_pwridx[1]); in _rtl92s_get_powerbase()
103 "20MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n", in _rtl92s_get_powerbase()
104 p_final_pwridx[0], p_final_pwridx[1]); in _rtl92s_get_powerbase()
114 s8 ant_pwr_diff = 0; in _rtl92s_set_antennadiff()
115 u32 u4reg_val = 0; in _rtl92s_set_antennadiff()
118 ant_pwr_diff = p_final_pwridx[1] - p_final_pwridx[0]; in _rtl92s_set_antennadiff()
121 * index = 0x0~0xf */ in _rtl92s_set_antennadiff()
128 "Antenna Diff from RF-B to RF-A = %d (0x%x)\n", in _rtl92s_set_antennadiff()
129 ant_pwr_diff, ant_pwr_diff & 0xf); in _rtl92s_set_antennadiff()
131 ant_pwr_diff &= 0xf; in _rtl92s_set_antennadiff()
135 rtlefuse->antenna_txpwdiff[2] = 0;/* RF-D, don't care */ in _rtl92s_set_antennadiff()
136 rtlefuse->antenna_txpwdiff[1] = 0;/* RF-C, don't care */ in _rtl92s_set_antennadiff()
137 rtlefuse->antenna_txpwdiff[0] = (u8)(ant_pwr_diff); /* RF-B */ in _rtl92s_set_antennadiff()
141 rtlefuse->antenna_txpwdiff[0]; in _rtl92s_set_antennadiff()
146 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Write BCD-Diff(0x%x) = 0x%x\n", in _rtl92s_set_antennadiff()
162 /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ in _rtl92s_get_txpower_writeval_byregulatory()
164 case 0: in _rtl92s_get_txpower_writeval_byregulatory()
167 chnlgroup = 0; in _rtl92s_get_txpower_writeval_byregulatory()
173 "RTK better performance, writeval = 0x%x\n", writeval); in _rtl92s_get_txpower_writeval_byregulatory()
182 "Realtek regulatory, 40MHz, writeval = 0x%x\n", in _rtl92s_get_txpower_writeval_byregulatory()
185 chnlgroup = 0; in _rtl92s_get_txpower_writeval_byregulatory()
189 chnlgroup = 0; in _rtl92s_get_txpower_writeval_byregulatory()
203 "Realtek regulatory, 20MHz, writeval = 0x%x\n", in _rtl92s_get_txpower_writeval_byregulatory()
211 "Better regulatory, writeval = 0x%x\n", writeval); in _rtl92s_get_txpower_writeval_byregulatory()
216 chnlgroup = 0; in _rtl92s_get_txpower_writeval_byregulatory()
220 "customer's limit, 40MHz = 0x%x\n", in _rtl92s_get_txpower_writeval_byregulatory()
225 "customer's limit, 20MHz = 0x%x\n", in _rtl92s_get_txpower_writeval_byregulatory()
230 for (i = 0; i < 4; i++) { in _rtl92s_get_txpower_writeval_byregulatory()
232 [chnlgroup][index] & (0x7f << (i * 8))) in _rtl92s_get_txpower_writeval_byregulatory()
258 (pwrdiff_limit[0]); in _rtl92s_get_txpower_writeval_byregulatory()
260 "Customer's limit = 0x%x\n", customer_limit); in _rtl92s_get_txpower_writeval_byregulatory()
265 "Customer, writeval = 0x%x\n", writeval); in _rtl92s_get_txpower_writeval_byregulatory()
268 chnlgroup = 0; in _rtl92s_get_txpower_writeval_byregulatory()
272 "RTK better performance, writeval = 0x%x\n", writeval); in _rtl92s_get_txpower_writeval_byregulatory()
277 writeval = 0x10101010; in _rtl92s_get_txpower_writeval_byregulatory()
280 writeval = 0x0; in _rtl92s_get_txpower_writeval_byregulatory()
292 u16 regoffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; in _rtl92s_write_ofdm_powerreg()
294 u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0; in _rtl92s_write_ofdm_powerreg()
301 rf_pwr_diff = rtlefuse->antenna_txpwdiff[0]; in _rtl92s_write_ofdm_powerreg()
306 rfa_lower_bound = 0x10 - rf_pwr_diff; in _rtl92s_write_ofdm_powerreg()
307 /* if (rf_pwr_diff >= 0) Diff = 0-7 */ in _rtl92s_write_ofdm_powerreg()
313 for (i = 0; i < 4; i++) { in _rtl92s_write_ofdm_powerreg()
314 rfa_pwr[i] = (u8)((writeval & (0x7f << (i * 8))) >> (i * 8)); in _rtl92s_write_ofdm_powerreg()
327 /* Diff = 0-7 */ in _rtl92s_write_ofdm_powerreg()
338 rfa_pwr[0]; in _rtl92s_write_ofdm_powerreg()
340 rtl_set_bbreg(hw, regoffset[index], 0x7f7f7f7f, writeval); in _rtl92s_write_ofdm_powerreg()
347 u8 index = 0; in rtl92s_phy_rf6052_set_ofdmtxpower()
351 &finalpwr_idx[0]); in rtl92s_phy_rf6052_set_ofdmtxpower()
352 _rtl92s_set_antennadiff(hw, &finalpwr_idx[0]); in rtl92s_phy_rf6052_set_ofdmtxpower()
354 for (index = 0; index < 6; index++) { in rtl92s_phy_rf6052_set_ofdmtxpower()
367 u32 txagc = 0; in rtl92s_phy_rf6052_set_ccktxpower()
373 (rtlefuse->eeprom_regulatory != 0))) in rtl92s_phy_rf6052_set_ccktxpower()
377 txagc = 0x3f; in rtl92s_phy_rf6052_set_ccktxpower()
385 txagc = 0x10; in rtl92s_phy_rf6052_set_ccktxpower()
388 txagc = 0x0; in rtl92s_phy_rf6052_set_ccktxpower()
402 u32 u4reg_val = 0; in rtl92s_phy_rf6052_config()
408 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { in rtl92s_phy_rf6052_config()
430 BRFSI_RFENV << 16, 0x1); in rtl92s_phy_rf6052_config()
433 rtl92s_phy_set_bb_reg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in rtl92s_phy_rf6052_config()
437 B3WIRE_ADDRESSLENGTH, 0x0); in rtl92s_phy_rf6052_config()
439 B3WIRE_DATALENGTH, 0x0); in rtl92s_phy_rf6052_config()
492 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & in rtl92s_phy_rf6052_set_bandwidth()
493 0xfffff3ff) | 0x0400); in rtl92s_phy_rf6052_set_bandwidth()
495 rtlphy->rfreg_chnlval[0]); in rtl92s_phy_rf6052_set_bandwidth()
498 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & in rtl92s_phy_rf6052_set_bandwidth()
499 0xfffff3ff)); in rtl92s_phy_rf6052_set_bandwidth()
501 rtlphy->rfreg_chnlval[0]); in rtl92s_phy_rf6052_set_bandwidth()