1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
29 	 * 0 - Disable ASPM,  in rtl92ee_init_aspm_vars()
30 	 * 1 - Enable ASPM without Clock Req,  in rtl92ee_init_aspm_vars()
31 	 * 2 - Enable ASPM with Clock Req,  in rtl92ee_init_aspm_vars()
32 	 * 3 - Alwyas Enable ASPM with Clock Req,  in rtl92ee_init_aspm_vars()
33 	 * 4 - Always Enable ASPM without Clock Req.  in rtl92ee_init_aspm_vars()
36 	rtlpci->const_pci_aspm = 3;  in rtl92ee_init_aspm_vars()
38 	/*Setting for PCI-E device */  in rtl92ee_init_aspm_vars()
39 	rtlpci->const_devicepci_aspm_setting = 0x03;  in rtl92ee_init_aspm_vars()
41 	/*Setting for PCI-E bridge */  in rtl92ee_init_aspm_vars()
42 	rtlpci->const_hostpci_aspm_setting = 0x02;  in rtl92ee_init_aspm_vars()
46 	 * 0 - Default,  in rtl92ee_init_aspm_vars()
47 	 * 1 - From ASPM setting without low Mac Pwr,  in rtl92ee_init_aspm_vars()
48 	 * 2 - From ASPM setting with low Mac Pwr,  in rtl92ee_init_aspm_vars()
49 	 * 3 - Bus D3  in rtl92ee_init_aspm_vars()
52 	rtlpci->const_hwsw_rfoff_d3 = 0;  in rtl92ee_init_aspm_vars()
57 	 * 0 - Not support ASPM,  in rtl92ee_init_aspm_vars()
58 	 * 1 - Support ASPM,  in rtl92ee_init_aspm_vars()
59 	 * 2 - According to chipset.  in rtl92ee_init_aspm_vars()
61 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;  in rtl92ee_init_aspm_vars()
72 	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;  in rtl92ee_init_sw_vars()
73 	rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();  in rtl92ee_init_sw_vars()
75 	rtlpriv->dm.dm_initialgain_enable = true;  in rtl92ee_init_sw_vars()
76 	rtlpriv->dm.dm_flag = 0;  in rtl92ee_init_sw_vars()
77 	rtlpriv->dm.disable_framebursting = false;  in rtl92ee_init_sw_vars()
78 	rtlpci->transmit_config = CFENDFORM | BIT(15);  in rtl92ee_init_sw_vars()
81 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;  in rtl92ee_init_sw_vars()
82 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;  in rtl92ee_init_sw_vars()
83 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;  in rtl92ee_init_sw_vars()
85 	rtlpci->receive_config = (RCR_APPFCS			|  in rtl92ee_init_sw_vars()
98 	rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT		|  in rtl92ee_init_sw_vars()
109 	rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);  in rtl92ee_init_sw_vars()
112 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;  in rtl92ee_init_sw_vars()
113 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;  in rtl92ee_init_sw_vars()
114 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;  in rtl92ee_init_sw_vars()
115 	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;  in rtl92ee_init_sw_vars()
116 	if (rtlpriv->cfg->mod_params->disable_watchdog)  in rtl92ee_init_sw_vars()
118 	rtlpriv->psc.reg_fwctrl_lps = 3;  in rtl92ee_init_sw_vars()
119 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;  in rtl92ee_init_sw_vars()
125 	if (rtlpriv->psc.reg_fwctrl_lps == 1)  in rtl92ee_init_sw_vars()
126 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;  in rtl92ee_init_sw_vars()
127 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)  in rtl92ee_init_sw_vars()
128 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;  in rtl92ee_init_sw_vars()
129 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)  in rtl92ee_init_sw_vars()
130 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;  in rtl92ee_init_sw_vars()
133 	rtlpriv->rtlhal.earlymode_enable = false;  in rtl92ee_init_sw_vars()
136 	rtlpriv->psc.low_power_enable = false;  in rtl92ee_init_sw_vars()
139 	rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);  in rtl92ee_init_sw_vars()
140 	if (!rtlpriv->rtlhal.pfirmware) {  in rtl92ee_init_sw_vars()
148 	rtlpriv->max_fw_size = 0x8000;  in rtl92ee_init_sw_vars()
151 				      rtlpriv->io.dev, GFP_KERNEL, hw,  in rtl92ee_init_sw_vars()
155 		vfree(rtlpriv->rtlhal.pfirmware);  in rtl92ee_init_sw_vars()
156 		rtlpriv->rtlhal.pfirmware = NULL;  in rtl92ee_init_sw_vars()
167 	if (rtlpriv->rtlhal.pfirmware) {  in rtl92ee_deinit_sw_vars()
168 		vfree(rtlpriv->rtlhal.pfirmware);  in rtl92ee_deinit_sw_vars()
169 		rtlpriv->rtlhal.pfirmware = NULL;  in rtl92ee_deinit_sw_vars()
173 /* get bt coexist status */
364 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");