Lines Matching +full:clear +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
26 SNAP_HDR_LEN - \
97 #define WILC_SPI_WAKEUP_BIT BIT(1)
101 #define WILC1000_SPI_CLK_STATUS_BIT BIT(2)
105 #define WILC3000_SPI_CLK_STATUS_BIT BIT(2)
108 #define WILC_SPI_HOST_TO_FW_BIT BIT(0)
111 #define WILC_SPI_FW_TO_HOST_BIT BIT(0)
113 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
119 #define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1)
122 #define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
123 #define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1)
126 #define WILC_SDIO_CCCR_ABORT_RESET BIT(3)
130 #define WILC_SDIO_WAKEUP_BIT BIT(0)
134 #define WILC1000_SDIO_CLK_STATUS_BIT BIT(0)
141 #define WILC3000_SDIO_CLK_STATUS_BIT BIT(4)
152 #define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
155 #define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
177 #define WILC_GLOBAL_MODE_ENABLE_WIFI BIT(0)
178 #define WILC_PWR_SEQ_ENABLE_WIFI_SLEEP BIT(28)
180 #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
181 #define WILC_HAVE_USE_PMU BIT(1)
182 #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
183 #define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
184 #define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
185 #define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
186 #define WILC_HAVE_XTAL_24 BIT(6)
187 #define WILC_HAVE_DISABLE_WILC_UART BIT(7)
188 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
240 #define WILC_ABORT_REQ_BIT BIT(31)
249 #define VO_AC_ACM_STAT_FIELD BIT(24)
251 #define VI_AC_ACM_STAT_FIELD BIT(16)
253 #define BE_AC_ACM_STAT_FIELD BIT(8)
255 #define BK_AC_ACM_STAT_FIELD BIT(1)
257 #define WILC_PKT_HDR_CONFIG_FIELD BIT(31)
266 #define WILC_VMM_HDR_TYPE BIT(31)
267 #define WILC_VMM_HDR_MGMT_FIELD BIT(30)
272 #define WILC_VMM_ENTRY_AVAILABLE BIT(2)
288 #define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
289 #define INT_0 BIT(IRG_FLAGS_OFFSET)
290 #define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
291 #define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
292 #define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
293 #define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
294 #define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
301 /* IRQ Clear word */
302 /* 0: Clear INT0 */
303 /* 1: Clear INT1 */
304 /* 2: Clear INT2 */
305 /* 3: Clear INT3 */
306 /* 4: Clear INT4 */
307 /* 5: Clear INT5 */
312 #define CLR_INT0 BIT(0)
313 #define CLR_INT1 BIT(1)
314 #define CLR_INT2 BIT(2)
315 #define CLR_INT3 BIT(3)
316 #define CLR_INT4 BIT(4)
317 #define CLR_INT5 BIT(5)
318 #define SEL_VMM_TBL0 BIT(6)
319 #define SEL_VMM_TBL1 BIT(7)
320 #define EN_VMM BIT(8)
325 #define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)