26 	mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);  in mt76x2_mac_pbf_init()
27 	mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);  in mt76x2_mac_pbf_init()
34 	s8 offset = 0;  in mt76x2_fixup_xtal()
38 	offset = eep_val & 0x7f;  in mt76x2_fixup_xtal()
39 	if ((eep_val & 0xff) == 0xff)  in mt76x2_fixup_xtal()
40 		offset = 0;  in mt76x2_fixup_xtal()
41 	else if (eep_val & 0x80)  in mt76x2_fixup_xtal()
42 		offset = 0 - offset;  in mt76x2_fixup_xtal()
45 	if (eep_val == 0x00 || eep_val == 0xff) {  in mt76x2_fixup_xtal()
47 		eep_val &= 0xff;  in mt76x2_fixup_xtal()
49 		if (eep_val == 0x00 || eep_val == 0xff)  in mt76x2_fixup_xtal()
50 			eep_val = 0x14;  in mt76x2_fixup_xtal()
53 	eep_val &= 0x7f;  in mt76x2_fixup_xtal()
59 	case 0:  in mt76x2_fixup_xtal()
60 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);  in mt76x2_fixup_xtal()
63 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);  in mt76x2_fixup_xtal()
101 	mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);  in mt76x2_mac_reset()
104 	mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);  in mt76x2_mac_reset()
105 	mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);  in mt76x2_mac_reset()
107 	mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);  in mt76x2_mac_reset()
109 	mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);  in mt76x2_mac_reset()
115 		return 0;  in mt76x2_mac_reset()
117 	for (i = 0; i < 256 / 32; i++)  in mt76x2_mac_reset()
118 		mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);  in mt76x2_mac_reset()
120 	for (i = 0; i < 256; i++) {  in mt76x2_mac_reset()
121 		mt76x02_mac_wcid_setup(dev, i, 0, NULL);  in mt76x2_mac_reset()
122 		mt76_wr(dev, MT_WCID_TX_RATE(i), 0);  in mt76x2_mac_reset()
123 		mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0);  in mt76x2_mac_reset()
126 	for (i = 0; i < MT_MAX_VIFS; i++)  in mt76x2_mac_reset()
129 	for (i = 0; i < 16; i++)  in mt76x2_mac_reset()
130 		for (k = 0; k < 4; k++)  in mt76x2_mac_reset()
133 	for (i = 0; i < 16; i++)  in mt76x2_mac_reset()
138 	return 0;  in mt76x2_mac_reset()
144 	mt76_set(dev, 0x10130, BIT(0) | BIT(16));  in mt76x2_power_on_rf_patch()
147 	mt76_clear(dev, 0x1001c, 0xff);  in mt76x2_power_on_rf_patch()
148 	mt76_set(dev, 0x1001c, 0x30);  in mt76x2_power_on_rf_patch()
150 	mt76_wr(dev, 0x10014, 0x484f);  in mt76x2_power_on_rf_patch()
153 	mt76_set(dev, 0x10130, BIT(17));  in mt76x2_power_on_rf_patch()
156 	mt76_clear(dev, 0x10130, BIT(16));  in mt76x2_power_on_rf_patch()
159 	mt76_set(dev, 0x1014c, BIT(19) | BIT(20));  in mt76x2_power_on_rf_patch()
165 	int shift = unit ? 8 : 0;  in mt76x2_power_on_rf()
168 	mt76_set(dev, 0x10130, BIT(0) << shift);  in mt76x2_power_on_rf()
172 	mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);  in mt76x2_power_on_rf()
176 	mt76_clear(dev, 0x10130, BIT(2) << shift);  in mt76x2_power_on_rf()
181 	mt76_set(dev, 0x530, 0xf);  in mt76x2_power_on_rf()
198 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);  in mt76x2_power_on()
201 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);  in mt76x2_power_on()
204 	mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);  in mt76x2_power_on()
205 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);  in mt76x2_power_on()
208 	mt76_clear(dev, 0x11204, BIT(3));  in mt76x2_power_on()
211 	mt76_set(dev, 0x10080, BIT(0));  in mt76x2_power_on()
214 	mt76_clear(dev, 0x10064, BIT(18));  in mt76x2_power_on()
216 	mt76x2_power_on_rf(dev, 0);  in mt76x2_power_on()
268 	return 0;  in mt76x2_init_hardware()
314 	return 0;  in mt76x2_register_device()