16 	struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);  in mt76x02_pre_tbtt_tasklet()
17 	struct mt76_dev *mdev = &dev->mt76;  in mt76x02_pre_tbtt_tasklet()
78 		tasklet_enable(&dev->mt76.pre_tbtt_tasklet);  in mt76x02e_pre_tbtt_enable()
80 		tasklet_disable(&dev->mt76.pre_tbtt_tasklet);  in mt76x02e_pre_tbtt_enable()
143 	dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);  in mt76x02_tx_worker()
154 					       mt76.tx_napi);  in mt76x02_poll_tx()
159 	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);  in mt76x02_poll_tx()
166 	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);  in mt76x02_poll_tx()
170 	mt76_worker_schedule(&dev->mt76.tx_worker);  in mt76x02_poll_tx()
185 	status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);  in mt76x02_dma_init()
189 	dev->mt76.tx_worker.fn = mt76x02_tx_worker;  in mt76x02_dma_init()
190 	tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);  in mt76x02_dma_init()
195 	mt76_dma_attach(&dev->mt76);  in mt76x02_dma_init()
213 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,  in mt76x02_dma_init()
226 	ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,  in mt76x02_dma_init()
231 	q = &dev->mt76.q_rx[MT_RXQ_MAIN];  in mt76x02_dma_init()
242 	netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,  in mt76x02_dma_init()
244 	napi_enable(&dev->mt76.tx_napi);  in mt76x02_dma_init()
254 	dev = container_of(mdev, struct mt76x02_dev, mt76);  in mt76x02_rx_poll_complete()
265 	intr &= dev->mt76.mmio.irqmask;  in mt76x02_irq_handler()
271 	trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);  in mt76x02_irq_handler()
280 		napi_schedule(&dev->mt76.napi[0]);  in mt76x02_irq_handler()
283 		napi_schedule(&dev->mt76.napi[1]);  in mt76x02_irq_handler()
286 		tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);  in mt76x02_irq_handler()
290 		if (dev->mt76.csa_complete)  in mt76x02_irq_handler()
291 			mt76_csa_finish(&dev->mt76);  in mt76x02_irq_handler()
300 		napi_schedule(&dev->mt76.tx_napi);  in mt76x02_irq_handler()
314 	mt76x02_wait_for_wpdma(&dev->mt76, 1000);  in mt76x02_dma_enable()
341 	mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);  in mt76x02_mac_start()
360 		prev_dma_idx = dev->mt76.tx_dma_idx[i];  in mt76x02_tx_hang()
362 		dev->mt76.tx_dma_idx[i] = dma_idx;  in mt76x02_tx_hang()
398 	lockdep_assert_held(&dev->mt76.mutex);  in mt76x02_reset_state()
403 	ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);  in mt76x02_reset_state()
413 		wcid = rcu_dereference_protected(dev->mt76.wcid[i],  in mt76x02_reset_state()
414 					lockdep_is_held(&dev->mt76.mutex));  in mt76x02_reset_state()
418 		rcu_assign_pointer(dev->mt76.wcid[i], NULL);  in mt76x02_reset_state()
430 	dev->mt76.vif_mask = 0;  in mt76x02_reset_state()
431 	dev->mt76.beacon_mask = 0;  in mt76x02_reset_state()
436 	u32 mask = dev->mt76.mmio.irqmask;  in mt76x02_watchdog_reset()
437 	bool restart = dev->mt76.mcu_ops->mcu_restart;  in mt76x02_watchdog_reset()
440 	ieee80211_stop_queues(dev->mt76.hw);  in mt76x02_watchdog_reset()
443 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);  in mt76x02_watchdog_reset()
444 	mt76_worker_disable(&dev->mt76.tx_worker);  in mt76x02_watchdog_reset()
445 	napi_disable(&dev->mt76.tx_napi);  in mt76x02_watchdog_reset()
447 	mt76_for_each_q_rx(&dev->mt76, i) {  in mt76x02_watchdog_reset()
448 		napi_disable(&dev->mt76.napi[i]);  in mt76x02_watchdog_reset()
451 	mutex_lock(&dev->mt76.mutex);  in mt76x02_watchdog_reset()
457 	if (dev->mt76.beacon_mask)  in mt76x02_watchdog_reset()
478 	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);  in mt76x02_watchdog_reset()
482 	mt76_for_each_q_rx(&dev->mt76, i) {  in mt76x02_watchdog_reset()
486 	mt76_tx_status_check(&dev->mt76, true);  in mt76x02_watchdog_reset()
493 	if (dev->mt76.beacon_mask && !restart)  in mt76x02_watchdog_reset()
500 	mutex_unlock(&dev->mt76.mutex);  in mt76x02_watchdog_reset()
504 	mt76_worker_enable(&dev->mt76.tx_worker);  in mt76x02_watchdog_reset()
505 	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);  in mt76x02_watchdog_reset()
507 	napi_enable(&dev->mt76.tx_napi);  in mt76x02_watchdog_reset()
508 	mt76_for_each_q_rx(&dev->mt76, i) {  in mt76x02_watchdog_reset()
509 		napi_enable(&dev->mt76.napi[i]);  in mt76x02_watchdog_reset()
513 	napi_schedule(&dev->mt76.tx_napi);  in mt76x02_watchdog_reset()
514 	mt76_for_each_q_rx(&dev->mt76, i) {  in mt76x02_watchdog_reset()
515 		napi_schedule(&dev->mt76.napi[i]);  in mt76x02_watchdog_reset()
522 		ieee80211_restart_hw(dev->mt76.hw);  in mt76x02_watchdog_reset()
524 		ieee80211_wake_queues(dev->mt76.hw);  in mt76x02_watchdog_reset()
553 	memset(dev->mt76.tx_dma_idx, 0xff,  in mt76x02_check_tx_hang()
554 	       sizeof(dev->mt76.tx_dma_idx));  in mt76x02_check_tx_hang()