Lines Matching +full:0 +full:x80c00000
40 .tx_start_ptr = 0,
42 .tx_wrap_mask = 0,
44 .rx_wrap_mask = 0,
48 .ring_flag_sop = 0,
49 .ring_flag_eop = 0,
50 .ring_flag_xs_sop = 0,
51 .ring_flag_xs_eop = 0,
52 .ring_tx_start_ptr = 0,
53 .pfu_enabled = 0,
55 .msix_support = 0,
73 .tx_mask = 0x03FF0000,
74 .tx_wrap_mask = 0x07FF0000,
75 .rx_mask = 0x000003FF,
76 .rx_wrap_mask = 0x000007FF,
86 .sleep_cookie = 0,
89 .fw_dump_end = 0xcff,
90 .fw_dump_host_ready = 0xee,
91 .fw_dump_read_done = 0xfe,
92 .msix_support = 0,
102 .tx_rdptr = 0xC1A4,
103 .tx_wrptr = 0xC174,
104 .rx_rdptr = 0xC174,
105 .rx_wrptr = 0xC1A4,
110 .tx_mask = 0x0FFF0000,
111 .tx_wrap_mask = 0x1FFF0000,
112 .rx_mask = 0x00000FFF,
113 .rx_wrap_mask = 0x00001FFF,
123 .sleep_cookie = 0,
126 .fw_dump_end = 0xcff,
127 .fw_dump_host_ready = 0xcc,
128 .fw_dump_read_done = 0xdd,
129 .msix_support = 0,
133 {"ITCM", NULL, 0, 0xF0},
134 {"DTCM", NULL, 0, 0xF1},
135 {"SQRAM", NULL, 0, 0xF2},
136 {"IRAM", NULL, 0, 0xF3},
137 {"APU", NULL, 0, 0xF4},
138 {"CIU", NULL, 0, 0xF5},
139 {"ICU", NULL, 0, 0xF6},
140 {"MAC", NULL, 0, 0xF7},
144 {"DUMP", NULL, 0, 0xDD},
188 return 0; in mwifiex_pcie_probe_of()
209 return 0; in mwifiex_map_pci_memory()
238 return 0; in mwifiex_write_reg_rpt()
248 if (*data == 0xffffffff) in mwifiex_read_reg()
249 return 0xffffffff; in mwifiex_read_reg()
251 return 0; in mwifiex_read_reg()
262 return 0; in mwifiex_read_reg_byte()
280 "info: ACCESS_HW: sleep cookie=0x%x\n", in mwifiex_pcie_ok_to_access_hw()
310 return 0; in mwifiex_pcie_suspend()
330 return 0; in mwifiex_pcie_suspend()
349 return 0; in mwifiex_pcie_resume()
357 return 0; in mwifiex_pcie_resume()
366 return 0; in mwifiex_pcie_resume()
382 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", in mwifiex_pcie_probe()
421 return 0; in mwifiex_pcie_probe()
485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
523 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n", in mwifiex_pcie_reset_prepare()
559 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n", in mwifiex_pcie_reset_done()
603 int i = 0; in mwifiex_pcie_dev_wakeup_delay()
624 for (count = 0; count < max_delay_loop_cnt; count++) { in mwifiex_delay_for_sleep_cookie()
669 READ_ONCE(adapter->int_status) != 0, in mwifiex_pm_wakeup_card()
674 READ_ONCE(adapter->int_status) != 0, in mwifiex_pm_wakeup_card()
691 return 0; in mwifiex_pm_wakeup_card()
704 return 0; in mwifiex_pm_wakeup_card_complete()
716 mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 0x00000000); in mwifiex_pcie_disable_host_int()
718 atomic_set(&adapter->tx_hw_pending, 0); in mwifiex_pcie_disable_host_int()
733 return 0; in mwifiex_pcie_enable_host_int()
747 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_init_txq_ring()
753 memset(desc2, 0, sizeof(*desc2)); in mwifiex_init_txq_ring()
758 memset(desc, 0, sizeof(*desc)); in mwifiex_init_txq_ring()
762 return 0; in mwifiex_init_txq_ring()
779 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_init_rxq_ring()
812 desc2->offset = 0; in mwifiex_init_rxq_ring()
819 desc->flags = 0; in mwifiex_init_rxq_ring()
823 return 0; in mwifiex_init_rxq_ring()
838 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { in mwifiex_pcie_init_evt_ring()
867 desc->flags = 0; in mwifiex_pcie_init_evt_ring()
870 return 0; in mwifiex_pcie_init_evt_ring()
885 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_cleanup_txq_ring()
894 memset(desc2, 0, sizeof(*desc2)); in mwifiex_cleanup_txq_ring()
903 memset(desc, 0, sizeof(*desc)); in mwifiex_cleanup_txq_ring()
908 atomic_set(&adapter->tx_hw_pending, 0); in mwifiex_cleanup_txq_ring()
924 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_cleanup_rxq_ring()
933 memset(desc2, 0, sizeof(*desc2)); in mwifiex_cleanup_rxq_ring()
942 memset(desc, 0, sizeof(*desc)); in mwifiex_cleanup_rxq_ring()
960 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { in mwifiex_cleanup_evt_ring()
969 memset(desc, 0, sizeof(*desc)); in mwifiex_cleanup_evt_ring()
984 * pointer. The write pointer starts at 0 (zero) while the read pointer in mwifiex_pcie_create_txbd_ring()
987 card->txbd_wrptr = 0; in mwifiex_pcie_create_txbd_ring()
990 card->txbd_rdptr = 0; in mwifiex_pcie_create_txbd_ring()
1037 card->txbd_ring_size = 0; in mwifiex_pcie_delete_txbd_ring()
1038 card->txbd_wrptr = 0; in mwifiex_pcie_delete_txbd_ring()
1039 card->txbd_rdptr = 0 | reg->tx_rollover_ind; in mwifiex_pcie_delete_txbd_ring()
1041 card->txbd_ring_pbase = 0; in mwifiex_pcie_delete_txbd_ring()
1043 return 0; in mwifiex_pcie_delete_txbd_ring()
1057 * pointer. The write pointer starts at 0 (zero) while the read pointer in mwifiex_pcie_create_rxbd_ring()
1060 card->rxbd_wrptr = 0; in mwifiex_pcie_create_rxbd_ring()
1110 card->rxbd_ring_size = 0; in mwifiex_pcie_delete_rxbd_ring()
1111 card->rxbd_wrptr = 0; in mwifiex_pcie_delete_rxbd_ring()
1112 card->rxbd_rdptr = 0 | reg->rx_rollover_ind; in mwifiex_pcie_delete_rxbd_ring()
1114 card->rxbd_ring_pbase = 0; in mwifiex_pcie_delete_rxbd_ring()
1116 return 0; in mwifiex_pcie_delete_rxbd_ring()
1130 * pointer. The write pointer starts at 0 (zero) while the read pointer in mwifiex_pcie_create_evtbd_ring()
1133 card->evtbd_wrptr = 0; in mwifiex_pcie_create_evtbd_ring()
1179 card->evtbd_wrptr = 0; in mwifiex_pcie_delete_evtbd_ring()
1180 card->evtbd_rdptr = 0 | reg->evt_rollover_ind; in mwifiex_pcie_delete_evtbd_ring()
1181 card->evtbd_ring_size = 0; in mwifiex_pcie_delete_evtbd_ring()
1183 card->evtbd_ring_pbase = 0; in mwifiex_pcie_delete_evtbd_ring()
1185 return 0; in mwifiex_pcie_delete_evtbd_ring()
1212 return 0; in mwifiex_pcie_alloc_cmdrsp_buf()
1223 return 0; in mwifiex_pcie_delete_cmdrsp_buf()
1240 return 0; in mwifiex_pcie_delete_cmdrsp_buf()
1264 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie); in mwifiex_pcie_alloc_sleep_cookie_buf()
1266 return 0; in mwifiex_pcie_alloc_sleep_cookie_buf()
1277 return 0; in mwifiex_pcie_delete_sleep_cookie_buf()
1288 return 0; in mwifiex_pcie_delete_sleep_cookie_buf()
1315 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; in mwifiex_pcie_send_data_complete()
1332 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", in mwifiex_pcie_send_data_complete()
1356 mwifiex_write_data_complete(adapter, skb, 0, in mwifiex_pcie_send_data_complete()
1359 mwifiex_write_data_complete(adapter, skb, 0, 0); in mwifiex_pcie_send_data_complete()
1367 memset(desc2, 0, sizeof(*desc2)); in mwifiex_pcie_send_data_complete()
1370 memset(desc, 0, sizeof(*desc)); in mwifiex_pcie_send_data_complete()
1394 card->txbd_flush = 0; in mwifiex_pcie_send_data_complete()
1399 return 0; in mwifiex_pcie_send_data_complete()
1439 put_unaligned_le16((u16)skb->len, payload + 0); in mwifiex_pcie_send_data()
1456 desc2->offset = 0; in mwifiex_pcie_send_data()
1532 int ret = 0; in mwifiex_pcie_process_recv_data()
1618 desc2->offset = 0; in mwifiex_pcie_process_recv_data()
1624 desc->flags = 0; in mwifiex_pcie_process_recv_data()
1696 return 0; in mwifiex_pcie_send_boot_cmd()
1741 put_unaligned_le16((u16)skb->len, &payload[0]); in mwifiex_pcie_send_cmd()
1792 return 0; in mwifiex_pcie_send_cmd()
1803 int count = 0; in mwifiex_pcie_process_cmd_complete()
1869 mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0); in mwifiex_pcie_process_cmd_complete()
1873 mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0); in mwifiex_pcie_process_cmd_complete()
1876 return 0; in mwifiex_pcie_process_cmd_complete()
1895 return 0; in mwifiex_pcie_cmdrsp_complete()
1916 return 0; in mwifiex_pcie_process_event_ready()
1933 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", in mwifiex_pcie_process_event_ready()
1940 __le16 data_len = 0; in mwifiex_pcie_process_event_ready()
1952 memset(desc, 0, sizeof(*desc)); in mwifiex_pcie_process_event_ready()
1984 return 0; in mwifiex_pcie_process_event_ready()
2000 return 0; in mwifiex_pcie_event_complete()
2004 "event_complete: Invalid rdptr 0x%x\n", in mwifiex_pcie_event_complete()
2027 desc->flags = 0; in mwifiex_pcie_event_complete()
2042 "info: Updated <Rd: 0x%x, Wr: 0x%x>", in mwifiex_pcie_event_complete()
2060 * that is start with CMD1, return 0.
2066 u32 offset = 0, data_len, dnld_cmd; in mwifiex_extract_wifi_fw()
2067 int ret = 0; in mwifiex_extract_wifi_fw()
2099 return 0; in mwifiex_extract_wifi_fw()
2166 u32 offset = 0; in mwifiex_prog_fw_w_helper()
2168 u32 txlen, tx_blocks = 0, tries, len, val; in mwifiex_prog_fw_w_helper()
2169 u32 block_retry_cnt = 0; in mwifiex_prog_fw_w_helper()
2200 if (ret < 0) { in mwifiex_prog_fw_w_helper()
2211 u32 ireg_intr = 0; in mwifiex_prog_fw_w_helper()
2217 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { in mwifiex_prog_fw_w_helper()
2242 if (len & BIT(0)) { in mwifiex_prog_fw_w_helper()
2253 "helper: len = 0x%04X, txlen = %d\n", in mwifiex_prog_fw_w_helper()
2255 len &= ~BIT(0); in mwifiex_prog_fw_w_helper()
2256 /* Setting this to 0 to resend from same offset */ in mwifiex_prog_fw_w_helper()
2257 txlen = 0; in mwifiex_prog_fw_w_helper()
2259 block_retry_cnt = 0; in mwifiex_prog_fw_w_helper()
2284 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { in mwifiex_prog_fw_w_helper()
2317 ret = 0; in mwifiex_prog_fw_w_helper()
2330 int ret = 0; in mwifiex_check_fw_status()
2345 for (tries = 0; tries < poll_num; tries++) { in mwifiex_check_fw_status()
2350 ret = 0; in mwifiex_check_fw_status()
2358 ret = 0; in mwifiex_check_fw_status()
2374 u32 winner = 0; in mwifiex_check_winner_status()
2375 int ret = 0; in mwifiex_check_winner_status()
2412 if (card->msix_enable && msg_id >= 0) { in mwifiex_interrupt_status()
2421 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg) in mwifiex_interrupt_status()
2446 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg); in mwifiex_interrupt_status()
2501 u32 pcie_ireg = 0; in mwifiex_process_int_status()
2510 adapter->int_status = 0; in mwifiex_process_int_status()
2522 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { in mwifiex_process_int_status()
2573 return 0; in mwifiex_process_int_status()
2601 return 0; in mwifiex_pcie_host_to_card()
2620 return 0; in mwifiex_pcie_reg_dump()
2626 return 0; in mwifiex_pcie_reg_dump()
2631 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) { in mwifiex_pcie_reg_dump()
2633 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n", in mwifiex_pcie_reg_dump()
2660 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { in mwifiex_pcie_rdwr_firmware()
2686 u8 idx, i, read_reg, doneflag = 0; in mwifiex_pcie_fw_dump()
2693 for (idx = 0; idx < adapter->num_mem_types; idx++) { in mwifiex_pcie_fw_dump()
2701 entry->mem_size = 0; in mwifiex_pcie_fw_dump()
2715 if (fw_dump_num == 0) in mwifiex_pcie_fw_dump()
2721 for (idx = 0; idx < dump_num; idx++) { in mwifiex_pcie_fw_dump()
2724 memory_size = 0; in mwifiex_pcie_fw_dump()
2725 if (fw_dump_num != 0) { in mwifiex_pcie_fw_dump()
2731 for (i = 0; i < 4; i++) { in mwifiex_pcie_fw_dump()
2740 if (memory_size == 0) { in mwifiex_pcie_fw_dump()
2748 "%s_SIZE=0x%x\n", entry->mem_name, memory_size); in mwifiex_pcie_fw_dump()
2795 "%s done: size=0x%tx\n", in mwifiex_pcie_fw_dump()
2900 return 0; in mwifiex_pcie_alloc_buffers()
2951 ret = pci_request_region(pdev, 0, DRV_NAME); in mwifiex_init_pcie()
2953 pr_err("req_reg(0) error\n"); in mwifiex_init_pcie()
2956 card->pci_mmap = pci_iomap(pdev, 0, 0); in mwifiex_init_pcie()
2958 pr_err("iomap(0) error\n"); in mwifiex_init_pcie()
2967 card->pci_mmap1 = pci_iomap(pdev, 2, 0); in mwifiex_init_pcie()
2984 return 0; in mwifiex_init_pcie()
2993 pci_release_region(pdev, 0); in mwifiex_init_pcie()
3029 mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000); in mwifiex_cleanup_pcie()
3037 pci_release_region(pdev, 0); in mwifiex_cleanup_pcie()
3049 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) in mwifiex_pcie_request_irq()
3054 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) { in mwifiex_pcie_request_irq()
3059 mwifiex_pcie_interrupt, 0, in mwifiex_pcie_request_irq()
3069 for (j = 0; j < i; j++) in mwifiex_pcie_request_irq()
3076 return 0; in mwifiex_pcie_request_irq()
3081 if (pci_enable_msi(pdev) != 0) in mwifiex_pcie_request_irq()
3097 return 0; in mwifiex_pcie_request_irq()
3107 int revision_id = 0; in mwifiex_pcie_get_fw_name()
3116 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000); in mwifiex_pcie_get_fw_name()
3117 mwifiex_read_reg(adapter, 0x0c58, &revision_id); in mwifiex_pcie_get_fw_name()
3118 revision_id &= 0xff00; in mwifiex_pcie_get_fw_name()
3133 mwifiex_read_reg(adapter, 0x8, &revision_id); in mwifiex_pcie_get_fw_name()
3134 mwifiex_read_reg(adapter, 0x0cd0, &version); in mwifiex_pcie_get_fw_name()
3135 mwifiex_read_reg(adapter, 0x0cd4, &magic); in mwifiex_pcie_get_fw_name()
3136 revision_id &= 0xff; in mwifiex_pcie_get_fw_name()
3137 version &= 0x7; in mwifiex_pcie_get_fw_name()
3138 magic &= 0xff; in mwifiex_pcie_get_fw_name()
3172 return 0; in mwifiex_register_dev()
3188 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) in mwifiex_unregister_dev()
3191 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) in mwifiex_unregister_dev()
3195 card->msix_enable = 0; in mwifiex_unregister_dev()
3234 mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000); in mwifiex_pcie_down_dev()
3238 adapter->seq_num = 0; in mwifiex_pcie_down_dev()