Lines Matching full:trans
19 #include "iwl-trans.h"
37 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) in iwl_trans_pcie_dump_regs() argument
43 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_regs()
67 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); in iwl_trans_pcie_dump_regs()
71 IWL_ERR(trans, "iwlwifi device config registers:\n"); in iwl_trans_pcie_dump_regs()
77 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); in iwl_trans_pcie_dump_regs()
79 *ptr = iwl_read32(trans, i); in iwl_trans_pcie_dump_regs()
84 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); in iwl_trans_pcie_dump_regs()
99 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", in iwl_trans_pcie_dump_regs()
112 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", in iwl_trans_pcie_dump_regs()
125 IWL_ERR(trans, "Read failed at 0x%X\n", i); in iwl_trans_pcie_dump_regs()
131 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership) in iwl_trans_pcie_sw_reset() argument
134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_trans_pcie_sw_reset()
135 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_sw_reset()
139 iwl_set_bit(trans, CSR_RESET, in iwl_trans_pcie_sw_reset()
145 return iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_sw_reset()
150 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) in iwl_pcie_free_fw_monitor() argument
152 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
157 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
165 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, in iwl_pcie_alloc_fw_monitor_block() argument
168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
182 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
187 IWL_INFO(trans, in iwl_pcie_alloc_fw_monitor_block()
197 IWL_ERR(trans, in iwl_pcie_alloc_fw_monitor_block()
207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) in iwl_pcie_alloc_fw_monitor() argument
221 iwl_pcie_alloc_fw_monitor_block(trans, max_power); in iwl_pcie_alloc_fw_monitor()
224 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_shr() argument
226 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_read_shr()
228 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); in iwl_trans_pcie_read_shr()
231 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) in iwl_trans_pcie_write_shr() argument
233 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); in iwl_trans_pcie_write_shr()
234 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_write_shr()
238 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) in iwl_pcie_set_pwr() argument
240 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
243 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
244 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
248 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
256 void iwl_pcie_apm_config(struct iwl_trans *trans) in iwl_pcie_apm_config() argument
258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apm_config()
267 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); in iwl_pcie_apm_config()
270 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
273 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
274 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
276 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
284 static int iwl_pcie_apm_init(struct iwl_trans *trans) in iwl_pcie_apm_init() argument
288 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); in iwl_pcie_apm_init()
296 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
297 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
304 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
308 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); in iwl_pcie_apm_init()
314 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_init()
317 iwl_pcie_apm_config(trans); in iwl_pcie_apm_init()
320 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
321 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); in iwl_pcie_apm_init()
323 ret = iwl_finish_nic_init(trans); in iwl_pcie_apm_init()
327 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
342 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
343 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
344 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); in iwl_pcie_apm_init()
345 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
346 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
356 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
357 iwl_write_prph(trans, APMG_CLK_EN_REG, in iwl_pcie_apm_init()
362 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_init()
366 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, in iwl_pcie_apm_init()
370 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
382 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) in iwl_pcie_apm_lp_xtal_enable() argument
390 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
393 ret = iwl_trans_pcie_sw_reset(trans, true); in iwl_pcie_apm_lp_xtal_enable()
396 ret = iwl_finish_nic_init(trans); in iwl_pcie_apm_lp_xtal_enable()
400 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
409 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_lp_xtal_enable()
416 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, in iwl_pcie_apm_lp_xtal_enable()
418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
422 ret = iwl_trans_pcie_sw_reset(trans, true); in iwl_pcie_apm_lp_xtal_enable()
424 IWL_ERR(trans, in iwl_pcie_apm_lp_xtal_enable()
428 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); in iwl_pcie_apm_lp_xtal_enable()
429 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | in iwl_pcie_apm_lp_xtal_enable()
434 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); in iwl_pcie_apm_lp_xtal_enable()
435 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & in iwl_pcie_apm_lp_xtal_enable()
442 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_lp_xtal_enable()
449 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_lp_xtal_enable()
452 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
456 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
461 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
466 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) in iwl_pcie_apm_stop_master() argument
472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_apm_stop_master()
473 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_stop_master()
476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_stop_master()
482 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); in iwl_pcie_apm_stop_master()
484 ret = iwl_poll_bit(trans, CSR_RESET, in iwl_pcie_apm_stop_master()
490 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); in iwl_pcie_apm_stop_master()
492 IWL_DEBUG_INFO(trans, "stop master\n"); in iwl_pcie_apm_stop_master()
495 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) in iwl_pcie_apm_stop() argument
497 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); in iwl_pcie_apm_stop()
500 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
501 iwl_pcie_apm_init(trans); in iwl_pcie_apm_stop()
504 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
505 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_stop()
507 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
509 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_stop()
515 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
521 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
524 iwl_pcie_apm_stop_master(trans); in iwl_pcie_apm_stop()
526 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
527 iwl_pcie_apm_lp_xtal_enable(trans); in iwl_pcie_apm_stop()
531 iwl_trans_pcie_sw_reset(trans, false); in iwl_pcie_apm_stop()
537 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_stop()
540 static int iwl_pcie_nic_init(struct iwl_trans *trans) in iwl_pcie_nic_init() argument
542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_nic_init()
547 ret = iwl_pcie_apm_init(trans); in iwl_pcie_nic_init()
553 iwl_pcie_set_pwr(trans, false); in iwl_pcie_nic_init()
555 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
558 ret = iwl_pcie_rx_init(trans); in iwl_pcie_nic_init()
563 if (iwl_pcie_tx_init(trans)) { in iwl_pcie_nic_init()
564 iwl_pcie_rx_free(trans); in iwl_pcie_nic_init()
568 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
570 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); in iwl_pcie_nic_init()
571 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); in iwl_pcie_nic_init()
580 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) in iwl_pcie_set_hw_ready() argument
584 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
588 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
594 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); in iwl_pcie_set_hw_ready()
596 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); in iwl_pcie_set_hw_ready()
601 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) in iwl_pcie_prepare_card_hw() argument
606 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); in iwl_pcie_prepare_card_hw()
608 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
611 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
615 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_prepare_card_hw()
623 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_prepare_card_hw()
627 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
629 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
634 IWL_DEBUG_INFO(trans, in iwl_pcie_prepare_card_hw()
636 trans->csme_own = true; in iwl_pcie_prepare_card_hw()
637 if (trans->trans_cfg->device_family != in iwl_pcie_prepare_card_hw()
639 IWL_ERR(trans, in iwl_pcie_prepare_card_hw()
651 IWL_ERR(trans, "Couldn't prepare the card\n"); in iwl_pcie_prepare_card_hw()
659 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, in iwl_pcie_load_firmware_chunk_fh() argument
663 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
666 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
669 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
672 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
676 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
681 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
687 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, in iwl_pcie_load_firmware_chunk() argument
691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_firmware_chunk()
696 if (!iwl_trans_grab_nic_access(trans)) in iwl_pcie_load_firmware_chunk()
699 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, in iwl_pcie_load_firmware_chunk()
701 iwl_trans_release_nic_access(trans); in iwl_pcie_load_firmware_chunk()
706 IWL_ERR(trans, "Failed to load firmware chunk!\n"); in iwl_pcie_load_firmware_chunk()
707 iwl_trans_pcie_dump_regs(trans); in iwl_pcie_load_firmware_chunk()
714 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, in iwl_pcie_load_section() argument
722 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", in iwl_pcie_load_section()
725 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
728 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); in iwl_pcie_load_section()
730 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
748 iwl_set_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
752 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, in iwl_pcie_load_section()
756 iwl_clear_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
760 IWL_ERR(trans, in iwl_pcie_load_section()
767 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
771 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections_8000() argument
800 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections_8000()
806 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
811 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); in iwl_pcie_load_cpu_sections_8000()
813 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); in iwl_pcie_load_cpu_sections_8000()
820 iwl_enable_interrupts(trans); in iwl_pcie_load_cpu_sections_8000()
822 if (trans->trans_cfg->gen2) { in iwl_pcie_load_cpu_sections_8000()
824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
841 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections() argument
866 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections()
872 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
882 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) in iwl_pcie_apply_destination_ini() argument
886 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
889 if (!iwl_trans_dbg_ini_valid(trans)) in iwl_pcie_apply_destination_ini()
894 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); in iwl_pcie_apply_destination_ini()
896 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apply_destination_ini()
904 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
907 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
909 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", in iwl_pcie_apply_destination_ini()
912 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, in iwl_pcie_apply_destination_ini()
914 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, in iwl_pcie_apply_destination_ini()
919 void iwl_pcie_apply_destination(struct iwl_trans *trans) in iwl_pcie_apply_destination() argument
921 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
922 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
925 if (iwl_trans_dbg_ini_valid(trans)) { in iwl_pcie_apply_destination()
926 iwl_pcie_apply_destination_ini(trans); in iwl_pcie_apply_destination()
930 IWL_INFO(trans, "Applying debug destination %s\n", in iwl_pcie_apply_destination()
934 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
936 IWL_WARN(trans, "PCI should have external buffer debug\n"); in iwl_pcie_apply_destination()
938 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
944 iwl_write32(trans, addr, val); in iwl_pcie_apply_destination()
947 iwl_set_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
950 iwl_clear_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
953 iwl_write_prph(trans, addr, val); in iwl_pcie_apply_destination()
956 iwl_set_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
959 iwl_clear_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
962 if (iwl_read_prph(trans, addr) & BIT(val)) { in iwl_pcie_apply_destination()
963 IWL_ERR(trans, in iwl_pcie_apply_destination()
970 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
978 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, in iwl_pcie_load_given_ucode() argument
997 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode()
1001 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); in iwl_pcie_load_given_ucode()
1007 iwl_write_prph(trans, in iwl_pcie_load_given_ucode()
1012 ret = iwl_pcie_load_cpu_sections(trans, image, 2, in iwl_pcie_load_given_ucode()
1018 if (iwl_pcie_dbg_on(trans)) in iwl_pcie_load_given_ucode()
1019 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode()
1021 iwl_enable_interrupts(trans); in iwl_pcie_load_given_ucode()
1024 iwl_write32(trans, CSR_RESET, 0); in iwl_pcie_load_given_ucode()
1029 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, in iwl_pcie_load_given_ucode_8000() argument
1035 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode_8000()
1038 if (iwl_pcie_dbg_on(trans)) in iwl_pcie_load_given_ucode_8000()
1039 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode_8000()
1041 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", in iwl_pcie_load_given_ucode_8000()
1042 iwl_read_prph(trans, WFPM_GP2)); in iwl_pcie_load_given_ucode_8000()
1049 iwl_write_prph(trans, WFPM_GP2, 0x01010101); in iwl_pcie_load_given_ucode_8000()
1053 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); in iwl_pcie_load_given_ucode_8000()
1056 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, in iwl_pcie_load_given_ucode_8000()
1062 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, in iwl_pcie_load_given_ucode_8000()
1066 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) in iwl_pcie_check_hw_rf_kill() argument
1068 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_check_hw_rf_kill()
1069 bool hw_rfkill = iwl_is_rfkill_set(trans); in iwl_pcie_check_hw_rf_kill()
1070 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1074 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1075 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1077 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1079 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1082 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1085 iwl_trans_pcie_rf_kill(trans, report, false); in iwl_pcie_check_hw_rf_kill()
1132 static void iwl_pcie_map_list(struct iwl_trans *trans, in iwl_pcie_map_list() argument
1139 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); in iwl_pcie_map_list()
1140 iwl_clear_bit(trans, causes[i].mask_reg, in iwl_pcie_map_list()
1145 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) in iwl_pcie_map_non_rx_causes() argument
1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_map_non_rx_causes()
1154 iwl_pcie_map_list(trans, causes_list_common, in iwl_pcie_map_non_rx_causes()
1156 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_map_non_rx_causes()
1157 iwl_pcie_map_list(trans, causes_list_bz, in iwl_pcie_map_non_rx_causes()
1160 iwl_pcie_map_list(trans, causes_list_pre_bz, in iwl_pcie_map_non_rx_causes()
1164 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) in iwl_pcie_map_rx_causes() argument
1166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_map_rx_causes()
1178 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1179 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), in iwl_pcie_map_rx_causes()
1183 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); in iwl_pcie_map_rx_causes()
1188 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); in iwl_pcie_map_rx_causes()
1191 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); in iwl_pcie_map_rx_causes()
1196 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw() local
1199 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1200 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1201 iwl_write_umac_prph(trans, UREG_CHICK, in iwl_pcie_conf_msix_hw()
1210 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1211 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); in iwl_pcie_conf_msix_hw()
1220 iwl_pcie_map_rx_causes(trans); in iwl_pcie_conf_msix_hw()
1222 iwl_pcie_map_non_rx_causes(trans); in iwl_pcie_conf_msix_hw()
1227 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix() local
1234 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1236 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1240 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq) in _iwl_trans_pcie_stop_device() argument
1242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_stop_device()
1252 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1255 iwl_pcie_disable_ict(trans); in _iwl_trans_pcie_stop_device()
1264 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1265 IWL_DEBUG_INFO(trans, in _iwl_trans_pcie_stop_device()
1268 iwl_pcie_synchronize_irqs(trans); in _iwl_trans_pcie_stop_device()
1269 iwl_pcie_rx_napi_sync(trans); in _iwl_trans_pcie_stop_device()
1270 iwl_pcie_tx_stop(trans); in _iwl_trans_pcie_stop_device()
1271 iwl_pcie_rx_stop(trans); in _iwl_trans_pcie_stop_device()
1274 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1275 iwl_write_prph(trans, APMG_CLK_DIS_REG, in _iwl_trans_pcie_stop_device()
1282 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in _iwl_trans_pcie_stop_device()
1283 iwl_clear_bit(trans, CSR_GP_CNTRL, in _iwl_trans_pcie_stop_device()
1286 iwl_clear_bit(trans, CSR_GP_CNTRL, in _iwl_trans_pcie_stop_device()
1290 iwl_pcie_apm_stop(trans, false); in _iwl_trans_pcie_stop_device()
1293 iwl_trans_pcie_sw_reset(trans, true); in _iwl_trans_pcie_stop_device()
1311 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1314 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1315 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1316 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1322 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_stop_device()
1325 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) in iwl_pcie_synchronize_irqs() argument
1327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_synchronize_irqs()
1339 int iwl_trans_pcie_start_fw(struct iwl_trans *trans, in iwl_trans_pcie_start_fw() argument
1342 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_fw()
1347 if (iwl_pcie_prepare_card_hw(trans)) { in iwl_trans_pcie_start_fw()
1348 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_start_fw()
1352 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_start_fw()
1354 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1361 iwl_disable_interrupts(trans); in iwl_trans_pcie_start_fw()
1364 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_start_fw()
1369 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); in iwl_trans_pcie_start_fw()
1377 IWL_WARN(trans, in iwl_trans_pcie_start_fw()
1384 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1385 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, in iwl_trans_pcie_start_fw()
1389 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1391 ret = iwl_pcie_nic_init(trans); in iwl_trans_pcie_start_fw()
1393 IWL_ERR(trans, "Unable to init nic\n"); in iwl_trans_pcie_start_fw()
1404 iwl_enable_fw_load_int(trans); in iwl_trans_pcie_start_fw()
1407 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1408 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1411 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1412 ret = iwl_pcie_load_given_ucode_8000(trans, fw); in iwl_trans_pcie_start_fw()
1414 ret = iwl_pcie_load_given_ucode(trans, fw); in iwl_trans_pcie_start_fw()
1417 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); in iwl_trans_pcie_start_fw()
1426 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) in iwl_trans_pcie_fw_alive() argument
1428 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_fw_alive()
1429 iwl_pcie_tx_start(trans, scd_addr); in iwl_trans_pcie_fw_alive()
1432 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, in iwl_trans_pcie_handle_stop_rfkill() argument
1449 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_handle_stop_rfkill()
1451 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1452 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1454 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1455 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1458 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false); in iwl_trans_pcie_handle_stop_rfkill()
1461 void iwl_trans_pcie_stop_device(struct iwl_trans *trans) in iwl_trans_pcie_stop_device() argument
1463 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_stop_device()
1466 iwl_op_mode_time_point(trans->op_mode, in iwl_trans_pcie_stop_device()
1472 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1473 _iwl_trans_pcie_stop_device(trans, false); in iwl_trans_pcie_stop_device()
1474 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); in iwl_trans_pcie_stop_device()
1478 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq) in iwl_trans_pcie_rf_kill() argument
1481 IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rf_kill()
1485 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", in iwl_trans_pcie_rf_kill()
1487 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && in iwl_trans_pcie_rf_kill()
1488 !WARN_ON(trans->trans_cfg->gen2)) in iwl_trans_pcie_rf_kill()
1489 _iwl_trans_pcie_stop_device(trans, from_irq); in iwl_trans_pcie_rf_kill()
1492 static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, in iwl_pcie_d3_complete_suspend() argument
1495 iwl_disable_interrupts(trans); in iwl_pcie_d3_complete_suspend()
1504 iwl_pcie_disable_ict(trans); in iwl_pcie_d3_complete_suspend()
1506 iwl_pcie_synchronize_irqs(trans); in iwl_pcie_d3_complete_suspend()
1508 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_d3_complete_suspend()
1509 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_d3_complete_suspend()
1511 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_d3_complete_suspend()
1514 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_d3_complete_suspend()
1516 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_d3_complete_suspend()
1526 iwl_trans_pcie_tx_reset(trans); in iwl_pcie_d3_complete_suspend()
1529 iwl_pcie_set_pwr(trans, true); in iwl_pcie_d3_complete_suspend()
1532 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) in iwl_pcie_d3_handshake() argument
1534 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_d3_handshake()
1537 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) in iwl_pcie_d3_handshake()
1538 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, in iwl_pcie_d3_handshake()
1541 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_d3_handshake()
1542 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, in iwl_pcie_d3_handshake()
1555 IWL_ERR(trans, "Timeout %s D3\n", in iwl_pcie_d3_handshake()
1563 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset) in iwl_trans_pcie_d3_suspend() argument
1569 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_trans_pcie_d3_suspend()
1572 ret = iwl_pcie_d3_handshake(trans, true); in iwl_trans_pcie_d3_suspend()
1576 iwl_pcie_d3_complete_suspend(trans, test, reset); in iwl_trans_pcie_d3_suspend()
1581 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, in iwl_trans_pcie_d3_resume() argument
1585 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_d3_resume()
1590 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1596 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_d3_resume()
1597 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1600 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1603 ret = iwl_finish_nic_init(trans); in iwl_trans_pcie_d3_resume()
1616 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_d3_resume()
1617 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1619 iwl_pcie_set_pwr(trans, false); in iwl_trans_pcie_d3_resume()
1622 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1625 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_resume()
1627 ret = iwl_pcie_rx_init(trans); in iwl_trans_pcie_d3_resume()
1629 IWL_ERR(trans, in iwl_trans_pcie_d3_resume()
1635 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", in iwl_trans_pcie_d3_resume()
1636 iwl_read_umac_prph(trans, WFPM_GP2)); in iwl_trans_pcie_d3_resume()
1638 val = iwl_read32(trans, CSR_RESET); in iwl_trans_pcie_d3_resume()
1646 ret = iwl_pcie_d3_handshake(trans, false); in iwl_trans_pcie_d3_resume()
1648 trans->state = IWL_TRANS_NO_FW; in iwl_trans_pcie_d3_resume()
1655 struct iwl_trans *trans, in iwl_pcie_set_interrupt_capa() argument
1658 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_set_interrupt_capa()
1677 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1684 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1696 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1700 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1703 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1706 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1708 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); in iwl_pcie_set_interrupt_capa()
1710 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1729 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) in iwl_pcie_irq_set_affinity() argument
1733 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_irq_set_affinity()
1736 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1748 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1779 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1785 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1790 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) in iwl_trans_pcie_clear_persistence_bit() argument
1794 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1805 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); in iwl_trans_pcie_clear_persistence_bit()
1807 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); in iwl_trans_pcie_clear_persistence_bit()
1810 IWL_ERR(trans, in iwl_trans_pcie_clear_persistence_bit()
1814 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, in iwl_trans_pcie_clear_persistence_bit()
1821 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) in iwl_pcie_gen2_force_power_gating() argument
1825 ret = iwl_finish_nic_init(trans); in iwl_pcie_gen2_force_power_gating()
1829 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1832 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1836 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1839 return iwl_trans_pcie_sw_reset(trans, true); in iwl_pcie_gen2_force_power_gating()
1842 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) in _iwl_trans_pcie_start_hw() argument
1844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_start_hw()
1849 err = iwl_pcie_prepare_card_hw(trans); in _iwl_trans_pcie_start_hw()
1851 IWL_ERR(trans, "Error while preparing HW: %d\n", err); in _iwl_trans_pcie_start_hw()
1855 err = iwl_trans_pcie_clear_persistence_bit(trans); in _iwl_trans_pcie_start_hw()
1859 err = iwl_trans_pcie_sw_reset(trans, true); in _iwl_trans_pcie_start_hw()
1863 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1864 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1865 err = iwl_pcie_gen2_force_power_gating(trans); in _iwl_trans_pcie_start_hw()
1870 err = iwl_pcie_apm_init(trans); in _iwl_trans_pcie_start_hw()
1877 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_start_hw()
1885 iwl_pcie_check_hw_rf_kill(trans); in _iwl_trans_pcie_start_hw()
1890 int iwl_trans_pcie_start_hw(struct iwl_trans *trans) in iwl_trans_pcie_start_hw() argument
1892 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_hw()
1896 ret = _iwl_trans_pcie_start_hw(trans); in iwl_trans_pcie_start_hw()
1902 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) in iwl_trans_pcie_op_mode_leave() argument
1904 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_op_mode_leave()
1909 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1911 iwl_pcie_apm_stop(trans, true); in iwl_trans_pcie_op_mode_leave()
1913 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1915 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_op_mode_leave()
1919 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_op_mode_leave()
1922 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) in iwl_trans_pcie_write8() argument
1924 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1927 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) in iwl_trans_pcie_write32() argument
1929 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1932 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) in iwl_trans_pcie_read32() argument
1934 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1937 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) in iwl_trans_pcie_prph_msk() argument
1939 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1945 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_prph() argument
1947 u32 mask = iwl_trans_pcie_prph_msk(trans); in iwl_trans_pcie_read_prph()
1949 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, in iwl_trans_pcie_read_prph()
1951 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); in iwl_trans_pcie_read_prph()
1954 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val) in iwl_trans_pcie_write_prph() argument
1956 u32 mask = iwl_trans_pcie_prph_msk(trans); in iwl_trans_pcie_write_prph()
1958 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, in iwl_trans_pcie_write_prph()
1960 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); in iwl_trans_pcie_write_prph()
1963 void iwl_trans_pcie_configure(struct iwl_trans *trans, in iwl_trans_pcie_configure() argument
1966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_configure()
1969 iwl_pcie_free_rbs_pool(trans); in iwl_trans_pcie_configure()
1991 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1997 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1998 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
2027 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) in iwl_pcie_free_invalid_tx_cmd() argument
2029 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); in iwl_pcie_free_invalid_tx_cmd()
2032 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) in iwl_pcie_alloc_invalid_tx_cmd() argument
2043 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, in iwl_pcie_alloc_invalid_tx_cmd()
2047 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); in iwl_pcie_alloc_invalid_tx_cmd()
2051 void iwl_trans_pcie_free(struct iwl_trans *trans) in iwl_trans_pcie_free() argument
2053 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_free()
2056 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_free()
2058 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
2059 iwl_txq_gen2_tx_free(trans); in iwl_trans_pcie_free()
2061 iwl_pcie_tx_free(trans); in iwl_trans_pcie_free()
2062 iwl_pcie_rx_free(trans); in iwl_trans_pcie_free()
2078 iwl_pcie_free_ict(trans); in iwl_trans_pcie_free()
2083 iwl_pcie_free_invalid_tx_cmd(trans); in iwl_trans_pcie_free()
2085 iwl_pcie_free_fw_monitor(trans); in iwl_trans_pcie_free()
2088 trans->dev); in iwl_trans_pcie_free()
2090 trans->dev); in iwl_trans_pcie_free()
2106 iwl_trans_free(trans); in iwl_trans_pcie_free()
2349 void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode) in iwl_trans_pcie_reset() argument
2357 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_reset()
2360 if (trans->me_present && mode == IWL_RESET_MODE_PROD_RESET) { in iwl_trans_pcie_reset()
2362 if (trans->me_present < 0) in iwl_trans_pcie_reset()
2368 IWL_INFO(trans, "scheduling reset (mode=%d%s)\n", mode, msg); in iwl_trans_pcie_reset()
2370 iwl_pcie_dump_csr(trans); in iwl_trans_pcie_reset()
2379 IWL_ERR(trans, in iwl_trans_pcie_reset()
2391 * the trans will be freed and reallocated. in iwl_trans_pcie_reset()
2393 set_bit(STATUS_TRANS_DEAD, &trans->status); in iwl_trans_pcie_reset()
2395 removal->pdev = to_pci_dev(trans->dev); in iwl_trans_pcie_reset()
2397 removal->integrated = trans->trans_cfg->integrated; in iwl_trans_pcie_reset()
2408 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) in __iwl_trans_pcie_grab_nic_access() argument
2411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in __iwl_trans_pcie_grab_nic_access()
2417 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in __iwl_trans_pcie_grab_nic_access()
2425 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in __iwl_trans_pcie_grab_nic_access()
2432 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); in __iwl_trans_pcie_grab_nic_access()
2433 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in __iwl_trans_pcie_grab_nic_access()
2456 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); in __iwl_trans_pcie_grab_nic_access()
2458 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); in __iwl_trans_pcie_grab_nic_access()
2464 iwl_trans_pcie_dump_regs(trans); in __iwl_trans_pcie_grab_nic_access()
2467 iwl_trans_pcie_reset(trans, in __iwl_trans_pcie_grab_nic_access()
2470 iwl_write32(trans, CSR_RESET, in __iwl_trans_pcie_grab_nic_access()
2486 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) in iwl_trans_pcie_grab_nic_access() argument
2491 ret = __iwl_trans_pcie_grab_nic_access(trans); in iwl_trans_pcie_grab_nic_access()
2500 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) in iwl_trans_pcie_release_nic_access() argument
2502 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_release_nic_access()
2514 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_release_nic_access()
2515 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
2518 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
2530 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_read_mem() argument
2543 if (iwl_trans_grab_nic_access(trans)) { in iwl_trans_pcie_read_mem()
2544 iwl_write32(trans, HBUS_TARG_MEM_RADDR, in iwl_trans_pcie_read_mem()
2548 vals[offs] = iwl_read32(trans, in iwl_trans_pcie_read_mem()
2557 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_read_mem()
2568 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_read_mem()
2580 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_mem() argument
2586 if (iwl_trans_grab_nic_access(trans)) { in iwl_trans_pcie_write_mem()
2587 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); in iwl_trans_pcie_write_mem()
2589 iwl_write32(trans, HBUS_TARG_MEM_WDAT, in iwl_trans_pcie_write_mem()
2591 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_write_mem()
2598 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, in iwl_trans_pcie_read_config32() argument
2601 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2607 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, in iwl_trans_pcie_rxq_dma_data() argument
2610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rxq_dma_data()
2612 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2623 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) in iwl_trans_pcie_wait_txq_empty() argument
2625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_wait_txq_empty()
2632 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2638 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); in iwl_trans_pcie_wait_txq_empty()
2657 * trans layer (overflow TX) don't warn. in iwl_trans_pcie_wait_txq_empty()
2674 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
2676 iwl_txq_log_scd_error(trans, txq); in iwl_trans_pcie_wait_txq_empty()
2680 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); in iwl_trans_pcie_wait_txq_empty()
2685 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) in iwl_trans_pcie_wait_txqs_empty() argument
2687 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_wait_txqs_empty()
2693 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2703 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); in iwl_trans_pcie_wait_txqs_empty()
2711 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, in iwl_trans_pcie_set_bits_mask() argument
2714 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_set_bits_mask()
2717 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); in iwl_trans_pcie_set_bits_mask()
2755 void iwl_pcie_dump_csr(struct iwl_trans *trans) in iwl_pcie_dump_csr() argument
2784 IWL_ERR(trans, "CSR values:\n"); in iwl_pcie_dump_csr()
2785 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " in iwl_pcie_dump_csr()
2788 IWL_ERR(trans, " %25s: 0X%08x\n", in iwl_pcie_dump_csr()
2790 iwl_read32(trans, csr_tbl[i])); in iwl_pcie_dump_csr()
2797 debugfs_create_file(#name, mode, parent, trans, \
2825 struct iwl_trans *trans; member
2837 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2855 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2870 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show() local
2871 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_tx_queue_seq_show()
2911 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2919 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read() local
2920 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rx_queue_read()
2925 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2934 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2950 u32 r = iwl_get_closed_rb_stts(trans, rxq); in iwl_dbgfs_rx_queue_read()
2968 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read() local
2969 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_read()
3026 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write() local
3027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_write()
3045 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write() local
3047 iwl_pcie_dump_csr(trans); in iwl_dbgfs_csr_write()
3056 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read() local
3060 ret = iwl_dump_fh(trans, &buf); in iwl_dbgfs_fh_reg_read()
3074 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read() local
3075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rfkill_read()
3081 !(iwl_read32(trans, CSR_GP_CNTRL) & in iwl_dbgfs_rfkill_read()
3091 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write() local
3092 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rfkill_write()
3101 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
3104 iwl_pcie_handle_rfkill_irq(trans, false); in iwl_dbgfs_rfkill_write()
3112 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open() local
3113 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_monitor_data_open()
3115 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
3116 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
3117 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); in iwl_dbgfs_monitor_data_open()
3161 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read() local
3162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_monitor_data_read()
3163 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
3169 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
3171 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
3172 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
3178 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
3189 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); in iwl_dbgfs_monitor_data_read()
3190 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); in iwl_dbgfs_monitor_data_read()
3202 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
3220 IWL_WARN(trans, in iwl_dbgfs_monitor_data_read()
3224 IWL_WARN(trans, in iwl_dbgfs_monitor_data_read()
3244 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rf_read() local
3245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rf_read()
3259 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_reset_write() local
3284 iwl_trans_pcie_reset(trans, mode); in iwl_dbgfs_reset_write()
3312 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) in iwl_trans_pcie_dbgfs_register() argument
3314 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
3327 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) in iwl_trans_pcie_debugfs_cleanup() argument
3329 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_debugfs_cleanup()
3338 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) in iwl_trans_pcie_get_cmdlen() argument
3340 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_get_cmdlen()
3345 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); in iwl_trans_pcie_get_cmdlen()
3350 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, in iwl_trans_pcie_dump_rbs() argument
3354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_rbs()
3362 r = iwl_get_closed_rb_stts(trans, rxq); in iwl_trans_pcie_dump_rbs()
3370 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, in iwl_trans_pcie_dump_rbs()
3390 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, in iwl_trans_pcie_dump_csr() argument
3402 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_dump_csr()
3409 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, in iwl_trans_pcie_fh_regs_dump() argument
3416 if (!iwl_trans_grab_nic_access(trans)) in iwl_trans_pcie_fh_regs_dump()
3423 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3426 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_fh_regs_dump()
3428 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); in iwl_trans_pcie_fh_regs_dump()
3429 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); in iwl_trans_pcie_fh_regs_dump()
3431 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, in iwl_trans_pcie_fh_regs_dump()
3434 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_fh_regs_dump()
3442 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, in iwl_trans_pci_dump_marbh_monitor() argument
3450 if (!iwl_trans_grab_nic_access(trans)) in iwl_trans_pci_dump_marbh_monitor()
3453 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); in iwl_trans_pci_dump_marbh_monitor()
3455 buffer[i] = iwl_read_umac_prph_no_grab(trans, in iwl_trans_pci_dump_marbh_monitor()
3457 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); in iwl_trans_pci_dump_marbh_monitor()
3459 iwl_trans_release_nic_access(trans); in iwl_trans_pci_dump_marbh_monitor()
3465 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, in iwl_trans_pcie_dump_pointers() argument
3470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3475 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3476 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3477 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3478 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3485 write_ptr_val = iwl_read_prph(trans, write_ptr); in iwl_trans_pcie_dump_pointers()
3487 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); in iwl_trans_pcie_dump_pointers()
3489 cpu_to_le32(iwl_read_prph(trans, base)); in iwl_trans_pcie_dump_pointers()
3490 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3492 cpu_to_le32(iwl_read_prph(trans, base_high)); in iwl_trans_pcie_dump_pointers()
3501 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, in iwl_trans_pcie_dump_monitor() argument
3505 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3508 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3510 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3511 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3517 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); in iwl_trans_pcie_dump_monitor()
3523 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3529 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3530 base = (iwl_read_prph(trans, base) & in iwl_trans_pcie_dump_monitor()
3532 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3534 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3536 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_monitor()
3537 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3540 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3542 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3544 iwl_trans_pci_dump_marbh_monitor(trans, in iwl_trans_pcie_dump_monitor()
3559 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) in iwl_trans_get_fw_monitor_len() argument
3561 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3564 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3565 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3566 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3569 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3570 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3571 cfg_reg = iwl_read_prph(trans, cfg_reg); in iwl_trans_get_fw_monitor_len()
3573 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3575 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3579 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3582 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3583 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3585 base = iwl_read_prph(trans, base) << in iwl_trans_get_fw_monitor_len()
3586 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3587 end = iwl_read_prph(trans, end) << in iwl_trans_get_fw_monitor_len()
3588 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3591 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3593 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3594 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3606 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask, in iwl_trans_pcie_dump_data() argument
3610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_data()
3617 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3618 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3635 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); in iwl_trans_pcie_dump_data()
3643 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3645 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3646 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); in iwl_trans_pcie_dump_data()
3657 num_rbs = iwl_get_closed_rb_stts(trans, rxq); in iwl_trans_pcie_dump_data()
3665 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3666 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3669 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3690 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3695 cmdlen = iwl_trans_pcie_get_cmdlen(trans, in iwl_trans_pcie_dump_data()
3713 ptr = iwl_txq_dec_wrap(trans, ptr); in iwl_trans_pcie_dump_data()
3723 len += iwl_trans_pcie_dump_csr(trans, &data); in iwl_trans_pcie_dump_data()
3725 len += iwl_trans_pcie_fh_regs_dump(trans, &data); in iwl_trans_pcie_dump_data()
3727 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); in iwl_trans_pcie_dump_data()
3730 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3732 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3734 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3741 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3748 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); in iwl_trans_pcie_dump_data()
3755 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) in iwl_trans_pci_interrupts() argument
3758 iwl_enable_interrupts(trans); in iwl_trans_pci_interrupts()
3760 iwl_disable_interrupts(trans); in iwl_trans_pci_interrupts()
3763 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) in iwl_trans_pcie_sync_nmi() argument
3766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_sync_nmi()
3770 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_sync_nmi()
3779 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); in iwl_trans_pcie_sync_nmi()
3787 struct iwl_trans *trans; in iwl_trans_pcie_alloc() local
3803 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, in iwl_trans_pcie_alloc()
3805 if (!trans) in iwl_trans_pcie_alloc()
3808 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_alloc()
3810 if (trans->trans_cfg->gen2) { in iwl_trans_pcie_alloc()
3819 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); in iwl_trans_pcie_alloc()
3830 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_alloc()
3833 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_alloc()
3843 if (trans->trans_cfg->gen2) { in iwl_trans_pcie_alloc()
3845 dmam_pool_create("iwlwifi:bc", trans->dev, in iwl_trans_pcie_alloc()
3856 (trans->trans_cfg->gen2 ? 64 : 36)); in iwl_trans_pcie_alloc()
3870 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3932 iwl_disable_interrupts(trans); in iwl_trans_pcie_alloc()
3934 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3935 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3948 trans->hw_rev_step = trans->hw_rev & 0xF; in iwl_trans_pcie_alloc()
3950 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; in iwl_trans_pcie_alloc()
3952 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3954 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); in iwl_trans_pcie_alloc()
3955 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3956 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3961 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); in iwl_trans_pcie_alloc()
3970 ret = iwl_pcie_alloc_ict(trans); in iwl_trans_pcie_alloc()
3977 IRQF_SHARED, DRV_NAME, trans); in iwl_trans_pcie_alloc()
3979 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3989 iwl_dbg_tlv_init(trans); in iwl_trans_pcie_alloc()
3991 return trans; in iwl_trans_pcie_alloc()
3994 iwl_pcie_free_ict(trans); in iwl_trans_pcie_alloc()
4002 iwl_trans_free(trans); in iwl_trans_pcie_alloc()
4006 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, in iwl_trans_pcie_copy_imr_fh() argument
4009 iwl_write_prph(trans, IMR_UREG_CHICK, in iwl_trans_pcie_copy_imr_fh()
4010 iwl_read_prph(trans, IMR_UREG_CHICK) | in iwl_trans_pcie_copy_imr_fh()
4012 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); in iwl_trans_pcie_copy_imr_fh()
4013 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, in iwl_trans_pcie_copy_imr_fh()
4015 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, in iwl_trans_pcie_copy_imr_fh()
4017 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); in iwl_trans_pcie_copy_imr_fh()
4018 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, in iwl_trans_pcie_copy_imr_fh()
4024 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, in iwl_trans_pcie_copy_imr() argument
4027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_copy_imr()
4031 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); in iwl_trans_pcie_copy_imr()
4036 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); in iwl_trans_pcie_copy_imr()
4037 iwl_trans_pcie_dump_regs(trans); in iwl_trans_pcie_copy_imr()