Lines Matching +full:cmdq +full:- +full:sync
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
28 #include "mei/iwl-mei.h"
30 #include "iwl-fh.h"
31 #include "iwl-context-info-gen3.h"
44 struct pci_dev *pdev = trans_pcie->pci_dev; in iwl_trans_pcie_dump_regs()
48 if (trans_pcie->pcie_dbg_dumped_once) in iwl_trans_pcie_dump_regs()
65 prefix = (char *)buf + alloc_size - PREFIX_LEN; in iwl_trans_pcie_dump_regs()
93 if (!pdev->bus->self) in iwl_trans_pcie_dump_regs()
96 pdev = pdev->bus->self; in iwl_trans_pcie_dump_regs()
127 trans_pcie->pcie_dbg_dumped_once = 1; in iwl_trans_pcie_dump_regs()
133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ in iwl_trans_pcie_sw_reset()
134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_trans_pcie_sw_reset()
152 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
154 if (!fw_mon->size) in iwl_pcie_free_fw_monitor()
157 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
158 fw_mon->physical); in iwl_pcie_free_fw_monitor()
160 fw_mon->block = NULL; in iwl_pcie_free_fw_monitor()
161 fw_mon->physical = 0; in iwl_pcie_free_fw_monitor()
162 fw_mon->size = 0; in iwl_pcie_free_fw_monitor()
168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
174 if (fw_mon->size) { in iwl_pcie_alloc_fw_monitor_block()
175 memset(fw_mon->block, 0, fw_mon->size); in iwl_pcie_alloc_fw_monitor_block()
180 for (power = max_power; power >= 11; power--) { in iwl_pcie_alloc_fw_monitor_block()
182 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
198 "Sorry - debug buffer is only %luK while you requested %luK\n", in iwl_pcie_alloc_fw_monitor_block()
199 (unsigned long)BIT(power - 10), in iwl_pcie_alloc_fw_monitor_block()
200 (unsigned long)BIT(max_power - 10)); in iwl_pcie_alloc_fw_monitor_block()
202 fw_mon->block = block; in iwl_pcie_alloc_fw_monitor_block()
203 fw_mon->physical = physical; in iwl_pcie_alloc_fw_monitor_block()
204 fw_mon->size = size; in iwl_pcie_alloc_fw_monitor_block()
240 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
243 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
269 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); in iwl_pcie_apm_config()
270 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
272 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); in iwl_pcie_apm_config()
273 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
274 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
276 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
296 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
312 * wake device's PCI Express link L1a -> L0s in iwl_pcie_apm_init()
319 /* Configure analog phase-lock-loop before activating to D0A */ in iwl_pcie_apm_init()
320 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
327 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
329 * This is a bit of an abuse - This is needed for 7260 / 3160 in iwl_pcie_apm_init()
334 * consumes slightly more power (100uA) - but allows to be sure in iwl_pcie_apm_init()
356 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
361 /* Disable L1-Active */ in iwl_pcie_apm_init()
370 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
447 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_lp_xtal_enable()
472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_apm_stop_master()
500 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
504 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
507 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
521 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
526 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
535 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_stop()
546 spin_lock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
548 spin_unlock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
555 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
565 return -ENOMEM; in iwl_pcie_nic_init()
568 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
600 /* Note: returns standard 0/-ERROR code */
611 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
629 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
636 trans->csme_own = true; in iwl_pcie_prepare_card_hw()
637 if (trans->trans_cfg->device_family != in iwl_pcie_prepare_card_hw()
642 return -EBUSY; in iwl_pcie_prepare_card_hw()
694 trans_pcie->ucode_write_complete = false; in iwl_pcie_load_firmware_chunk()
697 return -EIO; in iwl_pcie_load_firmware_chunk()
703 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, in iwl_pcie_load_firmware_chunk()
704 trans_pcie->ucode_write_complete, 5 * HZ); in iwl_pcie_load_firmware_chunk()
708 return -ETIMEDOUT; in iwl_pcie_load_firmware_chunk()
719 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); in iwl_pcie_load_section()
725 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
730 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
733 return -ENOMEM; in iwl_pcie_load_section()
736 for (offset = 0; offset < section->len; offset += chunk_sz) { in iwl_pcie_load_section()
740 copy_size = min_t(u32, chunk_sz, section->len - offset); in iwl_pcie_load_section()
741 dst_addr = section->offset + offset; in iwl_pcie_load_section()
751 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); in iwl_pcie_load_section()
767 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
788 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections_8000()
792 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
794 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
797 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections_8000()
798 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections_8000()
799 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections_8000()
806 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
822 if (trans->trans_cfg->gen2) { in iwl_pcie_load_cpu_sections_8000()
854 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections()
858 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
860 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
863 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections()
864 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections()
865 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections()
872 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
886 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
892 if (le32_to_cpu(fw_mon_cfg->buf_location) == in iwl_pcie_apply_destination_ini()
902 if (le32_to_cpu(fw_mon_cfg->buf_location) != in iwl_pcie_apply_destination_ini()
904 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
907 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
913 frag->physical >> MON_BUFF_SHIFT_VER2); in iwl_pcie_apply_destination_ini()
915 (frag->physical + frag->size - 256) >> in iwl_pcie_apply_destination_ini()
921 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
922 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
931 get_fw_dbg_mode_string(dest->monitor_mode)); in iwl_pcie_apply_destination()
933 if (dest->monitor_mode == EXTERNAL_MODE) in iwl_pcie_apply_destination()
934 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
938 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
939 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); in iwl_pcie_apply_destination()
940 u32 val = le32_to_cpu(dest->reg_ops[i].val); in iwl_pcie_apply_destination()
942 switch (dest->reg_ops[i].op) { in iwl_pcie_apply_destination()
970 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
971 dest->reg_ops[i].op); in iwl_pcie_apply_destination()
977 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { in iwl_pcie_apply_destination()
978 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
979 fw_mon->physical >> dest->base_shift); in iwl_pcie_apply_destination()
980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
982 (fw_mon->physical + fw_mon->size - in iwl_pcie_apply_destination()
983 256) >> dest->end_shift); in iwl_pcie_apply_destination()
985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
986 (fw_mon->physical + fw_mon->size) >> in iwl_pcie_apply_destination()
987 dest->end_shift); in iwl_pcie_apply_destination()
998 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode()
1005 if (image->is_dual_cpus) { in iwl_pcie_load_given_ucode()
1036 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode_8000()
1070 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1074 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1075 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1077 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1078 if (trans_pcie->opmode_down) in iwl_pcie_check_hw_rf_kill()
1079 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1082 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1101 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \
1148 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; in iwl_pcie_map_non_rx_causes()
1152 * the first interrupt vector will serve non-RX and FBQ causes. in iwl_pcie_map_non_rx_causes()
1156 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_map_non_rx_causes()
1168 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; in iwl_pcie_map_rx_causes()
1172 * The first RX queue - fallback queue, which is designated for in iwl_pcie_map_rx_causes()
1175 * the other (N - 2) interrupt vectors. in iwl_pcie_map_rx_causes()
1178 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1180 MSIX_FH_INT_CAUSES_Q(idx - offset)); in iwl_pcie_map_rx_causes()
1186 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) in iwl_pcie_map_rx_causes()
1190 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) in iwl_pcie_map_rx_causes()
1196 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw()
1198 if (!trans_pcie->msix_enabled) { in iwl_pcie_conf_msix_hw()
1199 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1200 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1210 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1227 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix()
1231 if (!trans_pcie->msix_enabled) in iwl_pcie_init_msix()
1234 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1235 trans_pcie->fh_mask = trans_pcie->fh_init_mask; in iwl_pcie_init_msix()
1236 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1237 trans_pcie->hw_mask = trans_pcie->hw_init_mask; in iwl_pcie_init_msix()
1244 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_stop_device()
1246 if (trans_pcie->is_down) in _iwl_trans_pcie_stop_device()
1249 trans_pcie->is_down = true; in _iwl_trans_pcie_stop_device()
1264 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1273 /* Power-down device's busmaster DMA clocks */ in _iwl_trans_pcie_stop_device()
1274 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1282 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in _iwl_trans_pcie_stop_device()
1292 /* re-take ownership to prevent other users from stealing the device */ in _iwl_trans_pcie_stop_device()
1296 * Upon stop, the IVAR table gets erased, so msi-x won't in _iwl_trans_pcie_stop_device()
1297 * work. This causes a bug in RF-KILL flows, since the interrupt in _iwl_trans_pcie_stop_device()
1309 * should be masked. Re-ACK all the interrupts here. in _iwl_trans_pcie_stop_device()
1314 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1315 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1316 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1329 if (trans_pcie->msix_enabled) { in iwl_pcie_synchronize_irqs()
1332 for (i = 0; i < trans_pcie->alloc_vecs; i++) in iwl_pcie_synchronize_irqs()
1333 synchronize_irq(trans_pcie->msix_entries[i].vector); in iwl_pcie_synchronize_irqs()
1335 synchronize_irq(trans_pcie->pci_dev->irq); in iwl_pcie_synchronize_irqs()
1349 return -EIO; in iwl_trans_pcie_start_fw()
1357 * We enabled the RF-Kill interrupt and the handler may very in iwl_trans_pcie_start_fw()
1366 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1371 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1376 if (trans_pcie->is_down) { in iwl_trans_pcie_start_fw()
1379 ret = -EIO; in iwl_trans_pcie_start_fw()
1399 * by the RF-Kill interrupt (hence mask all the interrupt besides the in iwl_trans_pcie_start_fw()
1401 * RF-Kill switch is toggled, we will find out after having loaded in iwl_trans_pcie_start_fw()
1411 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1416 /* re-check RF-Kill state since we may have missed the interrupt */ in iwl_trans_pcie_start_fw()
1419 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1422 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1451 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1452 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1454 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1455 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1466 iwl_op_mode_time_point(trans->op_mode, in iwl_trans_pcie_stop_device()
1470 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1471 trans_pcie->opmode_down = true; in iwl_trans_pcie_stop_device()
1472 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1475 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1483 lockdep_assert_held(&trans_pcie->mutex); in iwl_trans_pcie_rf_kill()
1487 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && in iwl_trans_pcie_rf_kill()
1488 !WARN_ON(trans->trans_cfg->gen2)) in iwl_trans_pcie_rf_kill()
1508 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_d3_complete_suspend()
1522 * reset TX queues -- some of their registers reset during S3 in iwl_pcie_d3_complete_suspend()
1537 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) in iwl_pcie_d3_handshake()
1541 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_d3_handshake()
1548 ret = wait_event_timeout(trans_pcie->sx_waitq, in iwl_pcie_d3_handshake()
1549 trans_pcie->sx_complete, 2 * HZ); in iwl_pcie_d3_handshake()
1552 trans_pcie->sx_complete = false; in iwl_pcie_d3_handshake()
1557 return -ETIMEDOUT; in iwl_pcie_d3_handshake()
1596 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_d3_resume()
1610 * Also enables interrupts - none will happen as in iwl_trans_pcie_d3_resume()
1615 if (!trans_pcie->msix_enabled) in iwl_trans_pcie_d3_resume()
1648 trans->state = IWL_TRANS_NO_FW; in iwl_trans_pcie_d3_resume()
1663 if (!cfg_trans->mq_rx_supported) in iwl_pcie_set_interrupt_capa()
1666 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) in iwl_pcie_set_interrupt_capa()
1671 trans_pcie->msix_entries[i].entry = i; in iwl_pcie_set_interrupt_capa()
1673 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, in iwl_pcie_set_interrupt_capa()
1678 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", in iwl_pcie_set_interrupt_capa()
1682 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; in iwl_pcie_set_interrupt_capa()
1685 "MSI-X enabled. %d interrupt vectors were allocated\n", in iwl_pcie_set_interrupt_capa()
1695 if (num_irqs <= max_irqs - 2) { in iwl_pcie_set_interrupt_capa()
1696 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1697 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | in iwl_pcie_set_interrupt_capa()
1699 } else if (num_irqs == max_irqs - 1) { in iwl_pcie_set_interrupt_capa()
1700 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1701 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; in iwl_pcie_set_interrupt_capa()
1703 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1707 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", in iwl_pcie_set_interrupt_capa()
1708 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); in iwl_pcie_set_interrupt_capa()
1710 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1712 trans_pcie->alloc_vecs = num_irqs; in iwl_pcie_set_interrupt_capa()
1713 trans_pcie->msix_enabled = true; in iwl_pcie_set_interrupt_capa()
1719 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); in iwl_pcie_set_interrupt_capa()
1735 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; in iwl_pcie_irq_set_affinity()
1736 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1741 * (i.e. return will be > i - 1). in iwl_pcie_irq_set_affinity()
1743 cpu = cpumask_next(i - offset, cpu_online_mask); in iwl_pcie_irq_set_affinity()
1744 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1745 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, in iwl_pcie_irq_set_affinity()
1746 &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1748 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1750 trans_pcie->msix_entries[i].vector); in iwl_pcie_irq_set_affinity()
1760 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_pcie_init_msix_handler()
1763 const char *qname = queue_name(&pdev->dev, trans_pcie, i); in iwl_pcie_init_msix_handler()
1766 return -ENOMEM; in iwl_pcie_init_msix_handler()
1768 msix_entry = &trans_pcie->msix_entries[i]; in iwl_pcie_init_msix_handler()
1769 ret = devm_request_threaded_irq(&pdev->dev, in iwl_pcie_init_msix_handler()
1770 msix_entry->vector, in iwl_pcie_init_msix_handler()
1772 (i == trans_pcie->def_irq) ? in iwl_pcie_init_msix_handler()
1779 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1785 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1794 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1812 return -EPERM; in iwl_trans_pcie_clear_persistence_bit()
1847 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_start_hw()
1863 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1864 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1879 trans_pcie->opmode_down = false; in _iwl_trans_pcie_start_hw()
1882 trans_pcie->is_down = false; in _iwl_trans_pcie_start_hw()
1895 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1897 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1906 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1908 /* disable interrupts - don't enable HW RF kill interrupt */ in iwl_trans_pcie_op_mode_leave()
1917 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1924 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1929 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1934 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1939 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1968 /* free all first - we might be reconfigured for a different size */ in iwl_trans_pcie_configure()
1971 trans_pcie->txqs.cmd.q_id = trans_cfg->cmd_queue; in iwl_trans_pcie_configure()
1972 trans_pcie->txqs.cmd.fifo = trans_cfg->cmd_fifo; in iwl_trans_pcie_configure()
1973 trans_pcie->txqs.page_offs = trans_cfg->cb_data_offs; in iwl_trans_pcie_configure()
1974 trans_pcie->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); in iwl_trans_pcie_configure()
1975 trans_pcie->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; in iwl_trans_pcie_configure()
1977 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) in iwl_trans_pcie_configure()
1978 trans_pcie->n_no_reclaim_cmds = 0; in iwl_trans_pcie_configure()
1980 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; in iwl_trans_pcie_configure()
1981 if (trans_pcie->n_no_reclaim_cmds) in iwl_trans_pcie_configure()
1982 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, in iwl_trans_pcie_configure()
1983 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); in iwl_trans_pcie_configure()
1985 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; in iwl_trans_pcie_configure()
1986 trans_pcie->rx_page_order = in iwl_trans_pcie_configure()
1987 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1988 trans_pcie->rx_buf_bytes = in iwl_trans_pcie_configure()
1989 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1990 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); in iwl_trans_pcie_configure()
1991 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1992 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); in iwl_trans_pcie_configure()
1994 trans_pcie->txqs.bc_table_dword = trans_cfg->bc_table_dword; in iwl_trans_pcie_configure()
1995 trans_pcie->scd_set_active = trans_cfg->scd_set_active; in iwl_trans_pcie_configure()
1997 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1998 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
2001 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; in iwl_trans_pcie_configure()
2008 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; in iwl_trans_pcie_free_pnvm_dram_regions()
2011 for (i = 0; i < dram_regions->n_regions; i++) { in iwl_trans_pcie_free_pnvm_dram_regions()
2012 dma_free_coherent(dev, dram_regions->drams[i].size, in iwl_trans_pcie_free_pnvm_dram_regions()
2013 dram_regions->drams[i].block, in iwl_trans_pcie_free_pnvm_dram_regions()
2014 dram_regions->drams[i].physical); in iwl_trans_pcie_free_pnvm_dram_regions()
2016 dram_regions->n_regions = 0; in iwl_trans_pcie_free_pnvm_dram_regions()
2019 if (desc_dram->block) { in iwl_trans_pcie_free_pnvm_dram_regions()
2020 dma_free_coherent(dev, desc_dram->size, in iwl_trans_pcie_free_pnvm_dram_regions()
2021 desc_dram->block, in iwl_trans_pcie_free_pnvm_dram_regions()
2022 desc_dram->physical); in iwl_trans_pcie_free_pnvm_dram_regions()
2029 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); in iwl_pcie_free_invalid_tx_cmd()
2043 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, in iwl_pcie_alloc_invalid_tx_cmd()
2047 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); in iwl_pcie_alloc_invalid_tx_cmd()
2058 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
2064 if (trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_free()
2065 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_free()
2066 trans_pcie->rba.alloc_wq = NULL; in iwl_trans_pcie_free()
2069 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_free()
2070 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_trans_pcie_free()
2072 trans_pcie->msix_entries[i].vector, in iwl_trans_pcie_free()
2076 trans_pcie->msix_enabled = false; in iwl_trans_pcie_free()
2081 free_netdev(trans_pcie->napi_dev); in iwl_trans_pcie_free()
2087 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, in iwl_trans_pcie_free()
2088 trans->dev); in iwl_trans_pcie_free()
2089 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, in iwl_trans_pcie_free()
2090 trans->dev); in iwl_trans_pcie_free()
2092 mutex_destroy(&trans_pcie->mutex); in iwl_trans_pcie_free()
2094 if (trans_pcie->txqs.tso_hdr_page) { in iwl_trans_pcie_free()
2097 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i); in iwl_trans_pcie_free()
2099 if (p && p->page) in iwl_trans_pcie_free()
2100 __free_page(p->page); in iwl_trans_pcie_free()
2103 free_percpu(trans_pcie->txqs.tso_hdr_page); in iwl_trans_pcie_free()
2126 if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &dsm_guid, ACPI_DSM_REV, in iwl_trans_pcie_call_prod_reset_dsm()
2128 return ERR_PTR(-ENODEV); in iwl_trans_pcie_call_prod_reset_dsm()
2130 return iwl_acpi_get_dsm_object(&pdev->dev, ACPI_DSM_REV, in iwl_trans_pcie_call_prod_reset_dsm()
2134 return ERR_PTR(-EOPNOTSUPP); in iwl_trans_pcie_call_prod_reset_dsm()
2148 if (res->type != ACPI_TYPE_INTEGER) in iwl_trans_pcie_check_product_reset_mode()
2149 IWL_ERR_DEV(&pdev->dev, in iwl_trans_pcie_check_product_reset_mode()
2152 IWL_DEBUG_DEV_POWER(&pdev->dev, in iwl_trans_pcie_check_product_reset_mode()
2154 res->integer.value); in iwl_trans_pcie_check_product_reset_mode()
2174 IWL_ERR_DEV(&pdev->dev, in iwl_trans_pcie_set_product_reset()
2181 IWL_DEBUG_DEV_POWER(&pdev->dev, "%sabled product reset via DSM\n", in iwl_trans_pcie_set_product_reset()
2196 if (res->type != ACPI_TYPE_INTEGER) in iwl_trans_pcie_check_product_reset_status()
2197 IWL_ERR_DEV(&pdev->dev, in iwl_trans_pcie_check_product_reset_status()
2200 IWL_DEBUG_DEV_POWER(&pdev->dev, in iwl_trans_pcie_check_product_reset_status()
2202 res->integer.value); in iwl_trans_pcie_check_product_reset_status()
2213 int ret = -EINVAL; in iwl_trans_pcie_call_reset()
2215 status = acpi_evaluate_object(ACPI_HANDLE(&pdev->dev), in iwl_trans_pcie_call_reset()
2218 IWL_DEBUG_DEV_POWER(&pdev->dev, "No _PRR method found\n"); in iwl_trans_pcie_call_reset()
2223 if (p->type != ACPI_TYPE_PACKAGE || p->package.count != 1) { in iwl_trans_pcie_call_reset()
2228 ref = &p->package.elements[0]; in iwl_trans_pcie_call_reset()
2229 if (ref->type != ACPI_TYPE_LOCAL_REFERENCE) { in iwl_trans_pcie_call_reset()
2234 status = acpi_evaluate_object(ref->reference.handle, in iwl_trans_pcie_call_reset()
2246 IWL_DEBUG_DEV_POWER(&pdev->dev, "called _RST on _PRR object\n"); in iwl_trans_pcie_call_reset()
2249 IWL_DEBUG_DEV_POWER(&pdev->dev, in iwl_trans_pcie_call_reset()
2266 struct pci_dev *pdev = removal->pdev; in iwl_trans_pcie_removal_wk()
2272 bus = pdev->bus; in iwl_trans_pcie_removal_wk()
2277 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); in iwl_trans_pcie_removal_wk()
2279 if (removal->mode == IWL_RESET_MODE_PROD_RESET) { in iwl_trans_pcie_removal_wk()
2282 if (!removal->integrated) { in iwl_trans_pcie_removal_wk()
2284 int slot = PCI_SLOT(pdev->devfn); in iwl_trans_pcie_removal_wk()
2285 int func = PCI_FUNC(pdev->devfn); in iwl_trans_pcie_removal_wk()
2297 BT_DEV(0xE476), /* PTL-P */ in iwl_trans_pcie_removal_wk()
2298 BT_DEV(0xE376), /* PTL-H */ in iwl_trans_pcie_removal_wk()
2299 BT_DEV(0xD346), /* NVL-H */ in iwl_trans_pcie_removal_wk()
2300 BT_DEV(0x6E74), /* NVL-S */ in iwl_trans_pcie_removal_wk()
2302 BT_DEV(0xD246), /* RZL-H */ in iwl_trans_pcie_removal_wk()
2303 BT_DEV(0x6C46), /* RZL-M */ in iwl_trans_pcie_removal_wk()
2309 if (tmp->bus != bus) in iwl_trans_pcie_removal_wk()
2327 removal->mode == in iwl_trans_pcie_removal_wk()
2329 removal->integrated); in iwl_trans_pcie_removal_wk()
2330 if (removal->mode >= IWL_RESET_MODE_FUNC_RESET) in iwl_trans_pcie_removal_wk()
2336 if (removal->mode >= IWL_RESET_MODE_RESCAN) { in iwl_trans_pcie_removal_wk()
2337 if (bus->parent) in iwl_trans_pcie_removal_wk()
2338 bus = bus->parent; in iwl_trans_pcie_removal_wk()
2357 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_reset()
2360 if (trans->me_present && mode == IWL_RESET_MODE_PROD_RESET) { in iwl_trans_pcie_reset()
2362 if (trans->me_present < 0) in iwl_trans_pcie_reset()
2380 "Module is being unloaded - abort\n"); in iwl_trans_pcie_reset()
2393 set_bit(STATUS_TRANS_DEAD, &trans->status); in iwl_trans_pcie_reset()
2395 removal->pdev = to_pci_dev(trans->dev); in iwl_trans_pcie_reset()
2396 removal->mode = mode; in iwl_trans_pcie_reset()
2397 removal->integrated = trans->trans_cfg->integrated; in iwl_trans_pcie_reset()
2398 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); in iwl_trans_pcie_reset()
2399 pci_dev_get(removal->pdev); in iwl_trans_pcie_reset()
2400 schedule_work(&removal->work); in iwl_trans_pcie_reset()
2417 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in __iwl_trans_pcie_grab_nic_access()
2420 spin_lock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2422 if (trans_pcie->cmd_hold_nic_awake) in __iwl_trans_pcie_grab_nic_access()
2425 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in __iwl_trans_pcie_grab_nic_access()
2433 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in __iwl_trans_pcie_grab_nic_access()
2441 * host DRAM when sleeping/waking for power-saving. in __iwl_trans_pcie_grab_nic_access()
2453 * 5000 series and later (including 1000 series) have non-volatile SRAM, in __iwl_trans_pcie_grab_nic_access()
2473 spin_unlock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2479 * Fool sparse by faking we release the lock - sparse will in __iwl_trans_pcie_grab_nic_access()
2482 __release(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2504 lockdep_assert_held(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2507 * Fool sparse by faking we acquiring the lock - sparse will in iwl_trans_pcie_release_nic_access()
2510 __acquire(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2512 if (trans_pcie->cmd_hold_nic_awake) in iwl_trans_pcie_release_nic_access()
2514 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_release_nic_access()
2527 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2558 return -EIO; in iwl_trans_pcie_read_mem()
2573 return -EBUSY; in iwl_trans_pcie_read_mem()
2593 ret = -EBUSY; in iwl_trans_pcie_write_mem()
2601 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2612 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2613 return -EINVAL; in iwl_trans_pcie_rxq_dma_data()
2615 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; in iwl_trans_pcie_rxq_dma_data()
2616 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; in iwl_trans_pcie_rxq_dma_data()
2617 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; in iwl_trans_pcie_rxq_dma_data()
2618 data->fr_bd_wid = 0; in iwl_trans_pcie_rxq_dma_data()
2632 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2633 return -ENODEV; in iwl_trans_pcie_wait_txq_empty()
2635 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used)) in iwl_trans_pcie_wait_txq_empty()
2636 return -EINVAL; in iwl_trans_pcie_wait_txq_empty()
2639 txq = trans_pcie->txqs.txq[txq_idx]; in iwl_trans_pcie_wait_txq_empty()
2641 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2642 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2643 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2644 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2646 wr_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2648 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || in iwl_trans_pcie_wait_txq_empty()
2652 u8 write_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2660 "WR pointer moved while flushing %d -> %d\n", in iwl_trans_pcie_wait_txq_empty()
2662 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2667 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2668 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2669 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2670 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2673 if (txq->read_ptr != txq->write_ptr) { in iwl_trans_pcie_wait_txq_empty()
2677 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2693 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2696 if (cnt == trans_pcie->txqs.cmd.q_id) in iwl_trans_pcie_wait_txqs_empty()
2698 if (!test_bit(cnt, trans_pcie->txqs.queue_used)) in iwl_trans_pcie_wait_txqs_empty()
2716 spin_lock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2718 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2834 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_start()
2837 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2843 state->pos = *pos; in iwl_dbgfs_tx_queue_seq_start()
2850 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_next()
2853 *pos = ++state->pos; in iwl_dbgfs_tx_queue_seq_next()
2855 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2868 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_show()
2870 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show()
2872 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos]; in iwl_dbgfs_tx_queue_seq_show()
2875 (unsigned int)state->pos, in iwl_dbgfs_tx_queue_seq_show()
2876 !!test_bit(state->pos, trans_pcie->txqs.queue_used), in iwl_dbgfs_tx_queue_seq_show()
2877 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped)); in iwl_dbgfs_tx_queue_seq_show()
2881 txq->read_ptr, txq->write_ptr, in iwl_dbgfs_tx_queue_seq_show()
2882 txq->need_update, txq->frozen, in iwl_dbgfs_tx_queue_seq_show()
2883 txq->n_window, txq->ampdu); in iwl_dbgfs_tx_queue_seq_show()
2887 if (state->pos == trans_pcie->txqs.cmd.q_id) in iwl_dbgfs_tx_queue_seq_show()
2909 return -ENOMEM; in iwl_dbgfs_tx_queue_open()
2911 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2919 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read()
2925 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2927 if (!trans_pcie->rxq) in iwl_dbgfs_rx_queue_read()
2928 return -EAGAIN; in iwl_dbgfs_rx_queue_read()
2932 return -ENOMEM; in iwl_dbgfs_rx_queue_read()
2934 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2935 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; in iwl_dbgfs_rx_queue_read()
2937 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", in iwl_dbgfs_rx_queue_read()
2939 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", in iwl_dbgfs_rx_queue_read()
2940 rxq->read); in iwl_dbgfs_rx_queue_read()
2941 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", in iwl_dbgfs_rx_queue_read()
2942 rxq->write); in iwl_dbgfs_rx_queue_read()
2943 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", in iwl_dbgfs_rx_queue_read()
2944 rxq->write_actual); in iwl_dbgfs_rx_queue_read()
2945 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", in iwl_dbgfs_rx_queue_read()
2946 rxq->need_update); in iwl_dbgfs_rx_queue_read()
2947 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", in iwl_dbgfs_rx_queue_read()
2948 rxq->free_count); in iwl_dbgfs_rx_queue_read()
2949 if (rxq->rb_stts) { in iwl_dbgfs_rx_queue_read()
2951 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2954 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2968 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read()
2970 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_read()
2979 return -ENOMEM; in iwl_dbgfs_interrupt_read()
2981 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2984 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2985 isr_stats->hw); in iwl_dbgfs_interrupt_read()
2986 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2987 isr_stats->sw); in iwl_dbgfs_interrupt_read()
2988 if (isr_stats->sw || isr_stats->hw) { in iwl_dbgfs_interrupt_read()
2989 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2991 isr_stats->err_code); in iwl_dbgfs_interrupt_read()
2994 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2995 isr_stats->sch); in iwl_dbgfs_interrupt_read()
2996 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2997 isr_stats->alive); in iwl_dbgfs_interrupt_read()
2999 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
3000 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); in iwl_dbgfs_interrupt_read()
3002 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
3003 isr_stats->ctkill); in iwl_dbgfs_interrupt_read()
3005 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
3006 isr_stats->wakeup); in iwl_dbgfs_interrupt_read()
3008 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
3009 "Rx command responses:\t\t %u\n", isr_stats->rx); in iwl_dbgfs_interrupt_read()
3011 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
3012 isr_stats->tx); in iwl_dbgfs_interrupt_read()
3014 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", in iwl_dbgfs_interrupt_read()
3015 isr_stats->unhandled); in iwl_dbgfs_interrupt_read()
3026 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write()
3028 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_write()
3045 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write()
3056 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read()
3064 return -EINVAL; in iwl_dbgfs_fh_reg_read()
3074 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read()
3080 trans_pcie->debug_rfkill, in iwl_dbgfs_rfkill_read()
3091 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write()
3099 if (new_value == trans_pcie->debug_rfkill) in iwl_dbgfs_rfkill_write()
3101 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
3102 trans_pcie->debug_rfkill, new_value); in iwl_dbgfs_rfkill_write()
3103 trans_pcie->debug_rfkill = new_value; in iwl_dbgfs_rfkill_write()
3112 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open()
3115 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
3116 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
3118 return -ENOENT; in iwl_dbgfs_monitor_data_open()
3121 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) in iwl_dbgfs_monitor_data_open()
3122 return -EBUSY; in iwl_dbgfs_monitor_data_open()
3124 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; in iwl_dbgfs_monitor_data_open()
3132 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); in iwl_dbgfs_monitor_data_release()
3134 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) in iwl_dbgfs_monitor_data_release()
3135 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_dbgfs_monitor_data_release()
3143 ssize_t buf_size_left = count - *bytes_copied; in iwl_write_to_user_buf()
3145 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); in iwl_write_to_user_buf()
3149 *size -= copy_to_user(user_buf, buf, *size); in iwl_write_to_user_buf()
3161 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read()
3163 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
3164 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_dbgfs_monitor_data_read()
3169 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
3171 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
3172 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
3178 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
3181 mutex_lock(&data->mutex); in iwl_dbgfs_monitor_data_read()
3182 if (data->state == in iwl_dbgfs_monitor_data_read()
3184 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
3192 if (data->prev_wrap_cnt == wrap_cnt) { in iwl_dbgfs_monitor_data_read()
3193 size = write_ptr - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
3194 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
3198 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
3200 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
3201 write_ptr < data->prev_wr_ptr) { in iwl_dbgfs_monitor_data_read()
3202 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
3203 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
3207 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
3214 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
3215 data->prev_wrap_cnt++; in iwl_dbgfs_monitor_data_read()
3218 if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
3219 write_ptr > data->prev_wr_ptr) in iwl_dbgfs_monitor_data_read()
3222 else if (!unlikely(data->prev_wrap_cnt == 0 && in iwl_dbgfs_monitor_data_read()
3223 data->prev_wr_ptr == 0)) in iwl_dbgfs_monitor_data_read()
3225 "monitor data is out of sync, start copying from the beginning\n"); in iwl_dbgfs_monitor_data_read()
3231 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
3232 data->prev_wrap_cnt = wrap_cnt; in iwl_dbgfs_monitor_data_read()
3235 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
3244 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rf_read()
3247 if (!trans_pcie->rf_name[0]) in iwl_dbgfs_rf_read()
3248 return -ENODEV; in iwl_dbgfs_rf_read()
3251 trans_pcie->rf_name, in iwl_dbgfs_rf_read()
3252 strlen(trans_pcie->rf_name)); in iwl_dbgfs_rf_read()
3259 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_reset_write()
3271 if (count > sizeof(buf) - 1) in iwl_dbgfs_reset_write()
3272 return -EINVAL; in iwl_dbgfs_reset_write()
3275 return -EFAULT; in iwl_dbgfs_reset_write()
3282 return -EINVAL; in iwl_dbgfs_reset_write()
3314 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
3330 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_trans_pcie_debugfs_cleanup()
3332 mutex_lock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
3333 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; in iwl_trans_pcie_debugfs_cleanup()
3334 mutex_unlock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
3344 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++) in iwl_trans_pcie_get_cmdlen()
3355 int max_len = trans_pcie->rx_buf_bytes; in iwl_trans_pcie_dump_rbs()
3356 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_rbs()
3357 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_rbs()
3360 spin_lock_bh(&rxq->lock); in iwl_trans_pcie_dump_rbs()
3364 for (i = rxq->read, j = 0; in iwl_trans_pcie_dump_rbs()
3367 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; in iwl_trans_pcie_dump_rbs()
3370 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, in iwl_trans_pcie_dump_rbs()
3375 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); in iwl_trans_pcie_dump_rbs()
3376 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); in iwl_trans_pcie_dump_rbs()
3377 rb = (void *)(*data)->data; in iwl_trans_pcie_dump_rbs()
3378 rb->index = cpu_to_le32(i); in iwl_trans_pcie_dump_rbs()
3379 memcpy(rb->data, page_address(rxb->page), max_len); in iwl_trans_pcie_dump_rbs()
3384 spin_unlock_bh(&rxq->lock); in iwl_trans_pcie_dump_rbs()
3397 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); in iwl_trans_pcie_dump_csr()
3398 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); in iwl_trans_pcie_dump_csr()
3399 val = (void *)(*data)->data; in iwl_trans_pcie_dump_csr()
3412 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; in iwl_trans_pcie_fh_regs_dump()
3419 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); in iwl_trans_pcie_fh_regs_dump()
3420 (*data)->len = cpu_to_le32(fh_regs_len); in iwl_trans_pcie_fh_regs_dump()
3421 val = (void *)(*data)->data; in iwl_trans_pcie_fh_regs_dump()
3423 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3447 u32 *buffer = (u32 *)fw_mon_data->data; in iwl_trans_pci_dump_marbh_monitor()
3470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3475 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3476 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3477 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3478 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3486 fw_mon_data->fw_mon_cycle_cnt = in iwl_trans_pcie_dump_pointers()
3488 fw_mon_data->fw_mon_base_ptr = in iwl_trans_pcie_dump_pointers()
3490 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3491 fw_mon_data->fw_mon_base_high_ptr = in iwl_trans_pcie_dump_pointers()
3497 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); in iwl_trans_pcie_dump_pointers()
3505 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3508 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3509 (fw_mon->size && in iwl_trans_pcie_dump_monitor()
3510 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3511 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3514 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); in iwl_trans_pcie_dump_monitor()
3515 fw_mon_data = (void *)(*data)->data; in iwl_trans_pcie_dump_monitor()
3520 if (fw_mon->size) { in iwl_trans_pcie_dump_monitor()
3521 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); in iwl_trans_pcie_dump_monitor()
3522 monitor_len = fw_mon->size; in iwl_trans_pcie_dump_monitor()
3523 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3524 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); in iwl_trans_pcie_dump_monitor()
3529 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3532 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3534 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3537 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3540 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3542 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3548 /* Didn't match anything - output no monitor data */ in iwl_trans_pcie_dump_monitor()
3553 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); in iwl_trans_pcie_dump_monitor()
3561 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3564 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3565 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3566 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3569 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3570 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3573 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3575 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3579 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3582 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3583 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3586 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3588 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3591 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3593 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3594 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3595 monitor_len = end - base; in iwl_trans_get_fw_monitor_len()
3612 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]; in iwl_trans_pcie_dump_data() local
3617 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3618 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3628 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) in iwl_trans_pcie_dump_data()
3630 cmdq->n_window * (sizeof(*txcmd) + in iwl_trans_pcie_dump_data()
3643 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3645 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3649 (FH_MEM_UPPER_BOUND - in iwl_trans_pcie_dump_data()
3654 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_data()
3655 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_data()
3658 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; in iwl_trans_pcie_dump_data()
3661 (PAGE_SIZE << trans_pcie->rx_page_order)); in iwl_trans_pcie_dump_data()
3665 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3666 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3669 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3676 data = (void *)dump_data->data; in iwl_trans_pcie_dump_data()
3678 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { in iwl_trans_pcie_dump_data()
3679 u16 tfd_size = trans_pcie->txqs.tfd.size; in iwl_trans_pcie_dump_data()
3681 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); in iwl_trans_pcie_dump_data()
3682 txcmd = (void *)data->data; in iwl_trans_pcie_dump_data()
3683 spin_lock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3684 ptr = cmdq->write_ptr; in iwl_trans_pcie_dump_data()
3685 for (i = 0; i < cmdq->n_window; i++) { in iwl_trans_pcie_dump_data()
3686 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); in iwl_trans_pcie_dump_data()
3690 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3696 (u8 *)cmdq->tfds + in iwl_trans_pcie_dump_data()
3702 txcmd->cmdlen = cpu_to_le32(cmdlen); in iwl_trans_pcie_dump_data()
3703 txcmd->caplen = cpu_to_le32(caplen); in iwl_trans_pcie_dump_data()
3704 memcpy(txcmd->data, cmdq->entries[idx].cmd, in iwl_trans_pcie_dump_data()
3706 if (sanitize_ops && sanitize_ops->frob_hcmd) in iwl_trans_pcie_dump_data()
3707 sanitize_ops->frob_hcmd(sanitize_ctx, in iwl_trans_pcie_dump_data()
3708 txcmd->data, in iwl_trans_pcie_dump_data()
3710 txcmd = (void *)((u8 *)txcmd->data + caplen); in iwl_trans_pcie_dump_data()
3715 spin_unlock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3717 data->len = cpu_to_le32(len); in iwl_trans_pcie_dump_data()
3730 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3732 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3734 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3736 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); in iwl_trans_pcie_dump_data()
3737 data->len = cpu_to_le32(sizeof(*paging) + page_len); in iwl_trans_pcie_dump_data()
3738 paging = (void *)data->data; in iwl_trans_pcie_dump_data()
3739 paging->index = cpu_to_le32(i); in iwl_trans_pcie_dump_data()
3740 memcpy(paging->data, in iwl_trans_pcie_dump_data()
3741 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3750 dump_data->len = len; in iwl_trans_pcie_dump_data()
3768 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_sync_nmi()
3770 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_sync_nmi()
3803 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, in iwl_trans_pcie_alloc()
3806 return ERR_PTR(-ENOMEM); in iwl_trans_pcie_alloc()
3810 if (trans->trans_cfg->gen2) { in iwl_trans_pcie_alloc()
3811 trans_pcie->txqs.tfd.addr_size = 64; in iwl_trans_pcie_alloc()
3812 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS; in iwl_trans_pcie_alloc()
3813 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd); in iwl_trans_pcie_alloc()
3815 trans_pcie->txqs.tfd.addr_size = 36; in iwl_trans_pcie_alloc()
3816 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS; in iwl_trans_pcie_alloc()
3817 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd); in iwl_trans_pcie_alloc()
3819 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); in iwl_trans_pcie_alloc()
3822 trans_pcie->txqs.cmd.wdg_timeout = IWL_DEF_WD_TIMEOUT; in iwl_trans_pcie_alloc()
3824 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); in iwl_trans_pcie_alloc()
3825 if (!trans_pcie->txqs.tso_hdr_page) { in iwl_trans_pcie_alloc()
3826 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3830 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_alloc()
3831 trans_pcie->txqs.bc_tbl_size = in iwl_trans_pcie_alloc()
3833 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_alloc()
3834 trans_pcie->txqs.bc_tbl_size = in iwl_trans_pcie_alloc()
3837 trans_pcie->txqs.bc_tbl_size = sizeof(struct iwlagn_scd_bc_tbl); in iwl_trans_pcie_alloc()
3839 * For gen2 devices, we use a single allocation for each byte-count in iwl_trans_pcie_alloc()
3843 if (trans->trans_cfg->gen2) { in iwl_trans_pcie_alloc()
3844 trans_pcie->txqs.bc_pool = in iwl_trans_pcie_alloc()
3845 dmam_pool_create("iwlwifi:bc", trans->dev, in iwl_trans_pcie_alloc()
3846 trans_pcie->txqs.bc_tbl_size, in iwl_trans_pcie_alloc()
3848 if (!trans_pcie->txqs.bc_pool) { in iwl_trans_pcie_alloc()
3849 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3855 WARN_ON(trans_pcie->txqs.tfd.addr_size != in iwl_trans_pcie_alloc()
3856 (trans->trans_cfg->gen2 ? 64 : 36)); in iwl_trans_pcie_alloc()
3858 /* Initialize NAPI here - it should be before registering to mac80211 in iwl_trans_pcie_alloc()
3861 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *)); in iwl_trans_pcie_alloc()
3862 if (!trans_pcie->napi_dev) { in iwl_trans_pcie_alloc()
3863 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3867 priv = netdev_priv(trans_pcie->napi_dev); in iwl_trans_pcie_alloc()
3870 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3871 trans_pcie->opmode_down = true; in iwl_trans_pcie_alloc()
3872 spin_lock_init(&trans_pcie->irq_lock); in iwl_trans_pcie_alloc()
3873 spin_lock_init(&trans_pcie->reg_lock); in iwl_trans_pcie_alloc()
3874 spin_lock_init(&trans_pcie->alloc_page_lock); in iwl_trans_pcie_alloc()
3875 mutex_init(&trans_pcie->mutex); in iwl_trans_pcie_alloc()
3876 init_waitqueue_head(&trans_pcie->ucode_write_waitq); in iwl_trans_pcie_alloc()
3877 init_waitqueue_head(&trans_pcie->fw_reset_waitq); in iwl_trans_pcie_alloc()
3878 init_waitqueue_head(&trans_pcie->imr_waitq); in iwl_trans_pcie_alloc()
3880 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", in iwl_trans_pcie_alloc()
3882 if (!trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_alloc()
3883 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3886 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); in iwl_trans_pcie_alloc()
3888 trans_pcie->debug_rfkill = -1; in iwl_trans_pcie_alloc()
3890 if (!cfg_trans->base_params->pcie_l1_allowed) { in iwl_trans_pcie_alloc()
3892 * W/A - seems to solve weird behavior. We need to remove this in iwl_trans_pcie_alloc()
3903 addr_size = trans_pcie->txqs.tfd.addr_size; in iwl_trans_pcie_alloc()
3904 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); in iwl_trans_pcie_alloc()
3906 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in iwl_trans_pcie_alloc()
3909 dev_err(&pdev->dev, "No suitable DMA available\n"); in iwl_trans_pcie_alloc()
3916 dev_err(&pdev->dev, "Requesting all PCI BARs failed.\n"); in iwl_trans_pcie_alloc()
3920 trans_pcie->hw_base = pcim_iomap(pdev, 0, 0); in iwl_trans_pcie_alloc()
3921 if (!trans_pcie->hw_base) { in iwl_trans_pcie_alloc()
3922 dev_err(&pdev->dev, "Could not ioremap PCI BAR 0.\n"); in iwl_trans_pcie_alloc()
3923 ret = -ENODEV; in iwl_trans_pcie_alloc()
3931 trans_pcie->pci_dev = pdev; in iwl_trans_pcie_alloc()
3934 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3935 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3936 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); in iwl_trans_pcie_alloc()
3937 ret = -EIO; in iwl_trans_pcie_alloc()
3943 * changed, and now the revision step also includes bit 0-1 (no more in iwl_trans_pcie_alloc()
3944 * "dash" value). To keep hw_rev backwards compatible - we'll store it in iwl_trans_pcie_alloc()
3947 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_alloc()
3948 trans->hw_rev_step = trans->hw_rev & 0xF; in iwl_trans_pcie_alloc()
3950 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; in iwl_trans_pcie_alloc()
3952 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3955 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3956 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3957 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); in iwl_trans_pcie_alloc()
3959 init_waitqueue_head(&trans_pcie->sx_waitq); in iwl_trans_pcie_alloc()
3965 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_alloc()
3974 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, in iwl_trans_pcie_alloc()
3979 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3985 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_trans_pcie_alloc()
3986 mutex_init(&trans_pcie->fw_mon_data.mutex); in iwl_trans_pcie_alloc()
3996 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_alloc()
3998 free_netdev(trans_pcie->napi_dev); in iwl_trans_pcie_alloc()
4000 free_percpu(trans_pcie->txqs.tso_hdr_page); in iwl_trans_pcie_alloc()
4028 int ret = -1; in iwl_trans_pcie_copy_imr()
4030 trans_pcie->imr_status = IMR_D2S_REQUESTED; in iwl_trans_pcie_copy_imr()
4032 ret = wait_event_timeout(trans_pcie->imr_waitq, in iwl_trans_pcie_copy_imr()
4033 trans_pcie->imr_status != in iwl_trans_pcie_copy_imr()
4035 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { in iwl_trans_pcie_copy_imr()
4038 return -ETIMEDOUT; in iwl_trans_pcie_copy_imr()
4040 trans_pcie->imr_status = IMR_D2S_IDLE; in iwl_trans_pcie_copy_imr()