Lines Matching +full:256 +full:k

37  * of the buffer, which must be 4K aligned.  Once this is set up, the device
42  *  31-0:  Keep-warm buffer physical base address [35:4], must be 4K aligned
53  * bytes from one another.  Each TFD circular buffer in DRAM must be 256-byte
59  *  27-0: TFD CB physical base address [35:8], must be 256-byte aligned
97  * Define the maximum transfer size. (64 / 128 / 256)
160  * 1)  Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
163  *     (typically 4K, although 8K or 16K are also selectable by driver).
168  *     27-0:  Receive Buffer physical address bits [35:8], 256-byte aligned
210  * Due to this, the maximum number of filled RBs is 255, instead of 256.  To
229  *  27-0:  RBD CD physical base address [35:8], must be 256-byte aligned.
237  *         NOTE:  For 256-entry circular buffer, use only bits [7:0].
260  * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
263  * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
264  *        '10' 12K, '11' 16K.
564 #define RX_QUEUE_SIZE                         256
590 #define TFD_QUEUE_SIZE_MAX      (256)
664  * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
666  * contiguous 256 TFDs.
667  * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
668  * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
677  * of (4K - 4).  The concatenates all of a TFD's buffers into a single
680  * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
715 #define IWL_KW_SIZE 0x1000	/* 4k */